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1 typical a pplica t ion fea t ures descrip t ion high current supercapacitor backup controller and system monitor the lt c ? 3350 is a backup power controller that can charge and monitor a series stack of one to four supercapacitors. the ltc3350s synchronous step-down controller drives n - channel mosfet s for constant current/ constant voltage charging with programmable input current limit. in addition, the step-down converter can run in reverse as a step-up converter to deliver power from the supercapacitor stack to the backup supply rail. internal balancers eliminate the need for external balance resistors and each capacitor has a shunt regulator for overvoltage protection. the ltc3350 monitors system voltages, currents, stack capacitance and stack esr which can all be read over the i 2 c/ smbus. the dual ideal diode controller uses n-channel mosfets for low loss power paths from the input and supercapacitors to the backup system supply. the ltc3350 is available in a low profile 38-lead 5mm 7mm 0.75mm qfn surface mount package. high current supercapacitor charger and backup supply a pplica t ions n high efficiency synchronous step-down cc/cv charging of one to four series supercapacitors n step-up mode in backup provides greater utilization of stored energy in supercapacitors n 14- bit adc for monitoring system voltages/currents, capacitance and esr n active overvoltage protection shunts n internal active balancersno balance resistors n v in : 4.5v to 35v, v cap(n) : up to 5v per capacitor, charge/backup current: 10+a n programmable input current limit prioritizes system load over capacitor charge current n dual ideal diode powerpath? controller n all n-fet charger controller and powerpath controller n compact 38-lead 5mm 7mm qfn package n high current 12v ride-through ups n servers/mass storage/high availability systems l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. backup operation v in pfi outfb outfet tgate sw bgate icap vcap cap4 cap3 cap2 cap1 caprtn capfb infet voutsp voutsn i chg (step-down) i backup v cap < v out (step-up) v cap > v out (direct connect) v out ltc3350 10f v cap 10f 10f 10f 3350 ta01a i 2 c v in 2v/div v cap 2v/div v out 2v/div 400ms/div back page application circuit 0v 3350 ta01a p backup = 25w v out v cap v in ltc 3350 3350fb for more information www.linear.com/ltc3350
2 table o f c on t en t s features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 t ypical performance characteristics ................... 7 pin functions .............................................. 10 block diagram ............................................. 13 t iming diagram ........................................... 14 operation ................................................... 14 introduction ............................................................ 14 b idirectional switching controllerstep-down mode ...................................................................... 14 b idirectional switching controllerstep-up mode 15 ide al diodes ............................................................ 16 g ate drive supply (drv cc ) .................................... 17 un dervoltage lockout (uvlo) ............................... 17 rt o scillator and switching frequency .................. 17 i nput overvoltage protection ................................. 17 v cap dac ............................................................... 17 po wer-fail (pf) comparator .................................... 17 charge status indication ......................................... 17 capacitor voltage balancer .................................... 17 c apacitor shunt regulators .................................... 18 i 2 c/smbus and smbalert .................................... 18 an alog-to-digital converter .................................... 18 c apacitance and esr measurement ...................... 18 m onitor status register .......................................... 19 c harge status register ........................................... 20 l imit checking and alarms ..................................... 20 d ie temperature sensor ......................................... 20 g eneral purpose input ............................................ 20 applications information ................................ 21 d igital configuration ............................................... 21 c apacitor configuration .......................................... 21 ca pacitor shunt regulator programming ............... 21 s etting input and charge currents ......................... 21 l ow current charging and high current backup .... 22 s etting v cap voltage ............................................... 22 p ower-fail comparator input voltage threshold ... 22 s etting v out voltage in backup mode .................... 23 co mpensation ......................................................... 24 m inimum v cap voltage in backup mode ................. 24 op timizing supercapacitor energy storage capacity .. 25 ca pacitor selection procedure ............................... 26 i nductor selection ................................................... 26 c out and c cap capacitance .................................... 27 po wer mosfet selection ....................................... 28 sc hottky diode selection ........................................ 28 t op mosfet driver supply (c b , d b ) ....................... 29 int v cc /drv cc and ic power dissipation ............... 29 min imum on-time considerations .......................... 30 ideal diode mosfet selection ............................... 30 p cb layout considerations .................................... 30 register map .............................................. 32 register descriptions .................................... 33 t ypical applications ...................................... 39 package description ..................................... 44 revision history .......................................... 45 t ypical application ....................................... 46 related parts .............................................. 46 ltc 3350 3350fb for more information www.linear.com/ltc3350
3 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , voutsp , voutsn ............................... C 0.3 v to 40 v vcap .......................................................... C0. 3 v to 22 v cap 4- cap 3, cap 3- cap 2, cap 2- cap 1, cap 1- caprtn .......................................... C 0.3 v to 5.5 v drv cc , outfb , capfb , smbalert , capgd , pfo , gpi , sda , scl .................................. C 0.3 v to 5.5 v bst ......................................................... C 0.3 v to 45.5 v pfi ............................................................. C0. 3 v to 20 v cap _ slct 0, cap _ slct 1 ................................ C 0.3 to 3v bst to sw ................................................ C0. 3 v to 5.5 v voutsp to voutsn , icap to vcap ......... C 0.3 v to 0.3 v i intvcc ................................................................. 100 ma i cap (1,2,3,4) , i caprtn ............................................ 600 ma i capgd , i pfo , i smbalert ......................................... 10 ma op erating junction temperature range ( notes 2, 3) .............................................. C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 13 14 15 16 top view 39 pgnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1scl sda smbalert capgd vc capfb outfb sgnd rt gpi itst caprtn voutsp voutsn intv cc drv cc bgate bst tgate sw vcc2p5 icap vcap outfet pfo pfi cap_slct1 cap_slct0 v in infet voutm5 cap1 cap2 cap3 cap4 cfp cfn vcapp5 23 22 21 20 9 10 11 12 t jmax = 125c, v ja = 34c/w exposed pad ( pin 39) is pgnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3350euhf#pbf ltc3350euhf#trpbf 3350 38-lead (5mm w 7mm) plastic qfn C40c to 125c ltc3350iuhf#pbf ltc3350iuhf#trpbf 3350 38-lead (5mm w 7mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 3350 3350fb for more information www.linear.com/ltc3350
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v out = 12v, v drvcc = v intvcc unless otherwise noted. symbol parameter conditions min typ max units switching regulator v in input supply voltage l 4.5 35 v i q input quiescent current (note 4) 4 ma v capfbhi maximum regulated v cap feedback voltage v capdac full scale (1111b) l 1.188 1.176 1.200 1.200 1.212 1.224 v v v capfblo minimum regulated v cap feedback voltage v capdac zero scale (0000b) 0.628 0.638 0.647 v i capfb capfb input leakage current v capfb = 1.2v l C50 50 na v outfb regulated v out feedback voltage l 1.188 1.176 1.200 1.200 1.212 1.224 v v v outfb(th) outfet turn-off threshold falling threshold 1.27 1.3 1.33 v i outfb outfb input leakage current v outfb = 1.2v l C50 50 na v outbst v out voltage in step-up mode v in = 0v l 4.5 35 v v uvlo intv cc undervoltage lockout rising threshold falling threshold l l 3.85 4.3 4 4.45 v v v drvuvlo drv cc undervoltage lockout rising threshold falling threshold l l 3.75 4.2 3.9 4.35 v v v duvlo v in C v cap differential undervoltage lockout rising threshold falling threshold l l 145 55 185 90 225 125 mv mv v ovlo v in overvoltage lockout rising threshold falling threshold l l 37.7 36.3 38.6 37.2 39.5 38.1 v v v vcapp5 charge pump output voltage relative to v cap , 0v v cap 20v 5 v input current sense amplifier v snsi regulated input current sense voltage (voutsp C voutsn) l 31.36 31.04 32.00 32.00 32.64 32.96 mv mv charge current sense amplifier v snsc regulated charge current sense voltage (icap C vcap) v cap = 10v l 31.36 31.04 32.00 32.00 32.64 32.96 mv mv v cmc common mode range (icap, vcap) 0 20 v v peak peak inductor current sense voltage l 51 58 65 mv v rev reverse inductor current sense voltage step-down mode l 3.867 7 10 mv i icap icap pin current step-down mode, v snsc = 32mv step-up mode, v snsc = 32mv 30 135 a a error amplifier g mv v cap voltage loop transconductance 1 mmho g mc charge current loop transconductance 64 mho g mi input current loop transconductance 64 mho g mo v out voltage loop transconductance 400 mho oscillator f sw switching frequency r t = 107k l 495 490 500 500 505 510 khz khz maximum programmable frequency r t = 53.6k 1 mhz minimum programmable frequency r t = 267k 200 khz ltc 3350 3350fb for more information www.linear.com/ltc3350
5 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v out = 12v, v drvcc = v intvcc unless otherwise noted. symbol parameter conditions min typ max units dc max maximum duty cycle step-down mode step-up mode 97 87 98 93 99.5 % % gate drivers r up-tg tgate pull-up on-resistance 2 r down-tg tgate pull-down on-resistance 0.6 r up-bg bgate pull-up on-resistance 2 r down-bg bgate pull-down on-resistance 0.6 t r-tg tgate 10% to 90% rise time c load = 3.3nf 18 25 ns t f-tg tgate 10% to 90% fall time c load = 3.3nf 8 15 ns t r-bg bgate 10% to 90% rise time c load = 3.3nf 18 25 ns t f-bg bgate 10% to 90% fall time c load = 3.3nf 8 15 ns t no non-overlap time 50 ns t on(min) 85 ns intv cc linear regulator v intvcc internal v cc voltage 5.2v v in 35v 5 v ?v intvcc load regulation i intvcc = 50ma C1.5 C2.5 % powerpath/ideal diodes v fto forward turn-on voltage 65 mv v fr forward regulation 30 mv v rto reverse turn off C30 mv t if(on) infet rise time infet C v in > 3v, c infet = 3.3nf 560 s t if(off) infet fall time infet C v in < 1v, c infet = 3.3nf 1.5 s t of(on) outfet rise time outfet C v cap > 3v, c outfet = 3.3nf 0.13 s t of(off) outfet fall time outfet C v cap < 1v, c outfet = 3.3nf 0.26 s power-fail comparator v pfi(th) pfi input threshold (falling edge) l 1.147 1.17 1.193 v v pfi(hys) pfi hysteresis 30 mv i pfi pfi input leakage current v pfi = 0.5v l C50 50 na v pfo pfo output low voltage i sink = 5ma 200 mv i pfo pfo high-z leakage current v pfo = 5v l 1 a pfi falling to pfo low delay 85 ns pfi rising to pfo high delay 0.4 s capgd v capfb(th) capgd rising threshold as % of regulated v cap feedback voltage v capfb_dac = full scale (1111b) l 90 92 94 % v capfb(hys) capgd hysteresis at capfb as a % of regulated v cap feedback voltage v capfb_dac = full scale (1111b) 1.25 % v capgd capgd output low voltage i sink = 5ma 200 mv i capgd capgd high-z leakage current v capgd = 5v l 1 a ltc 3350 3350fb for more information www.linear.com/ltc3350
6 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v out = 12v, v drvcc = v intvcc unless otherwise noted. symbol parameter conditions min typ max units analog-to-digital converter v res measurement resolution 16 bits v gpi general purpose input voltage range unbuffered buffered 0 0 5 3.5 v v i gpi general purpose input pin leakage current buffered input 1 a r gpi gpi pin resistance buffer disabled 2.5 m measurement system error v err measurement error (note 5) v in = 0v v in = 30v 100 1.5 mv % v outsp = 5v v outsp = 30v 100 1.5 mv % v cap = 0v v cap = 10v 100 1.5 mv % v gpi = 0v, unbuffered v gpi = 3.5v, unbuffered 2 1 mv % v cap1 = 0v v cap1 = 2v 2 1 mv % v cap2 = 0v v cap2 = 2v 2 1 mv % v cap3 = 0v v cap3 = 2v 2 1 mv % v cap4 = 0v v cap4 = 2v 2 1 mv % v snsi = 0mv v snsi = 32mv 200 2 v % v snsc = 0mv v snsc = 32mv 200 2 v % cap1 to cap4 r shnt shunt resistance 0.5 dv capmax maximum capacitor voltage with shunts enabled 2 or more capacitors in stack 3.6 v programming pins v itst itst voltage r tst = 121 1.185 1.197 1.209 v i 2 c/smbus C sda, scl, smbalert i il,sda,scl input leakage low C1 1 a i ih,sda,scl input leakage high C1 1 a v ih input high threshold 1.5 v v il input low threshold 0.8 v f scl scl clock frequency 400 khz t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t buf bus free time between start and stop conditions 1.3 s t hd, sta hold time, after (repeated) start condition 0.6 s t su, sta setup time after a repeated start condition 0.6 s ltc 3350 3350fb for more information www.linear.com/ltc3350
7 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v out = 12v, v drvcc = v intvcc unless otherwise noted. symbol parameter conditions min typ max units t su,sto stop condition set-up time 0.6 s t hd,dato output data hold time 0 900 ns t hd,dati input data hold time 0 ns t su, dat data set-up time 100 ns t sp input spike suppression pulse width 50 ns v smbalert smbalert output low voltage i sink = 1ma 200 mv i smbalert smbalert high-z leakage current v smbalert = 5v l 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3350 is tested under pulsed load conditions such that t j t a . the ltc3350e is guaranteed to meet specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3350i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 34c/w for the uhf package. note 3: the ltc3350 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125?c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 5: measurement error is the magnitude of the difference between the actual measured value and the ideal value. v snsi is the voltage between voutsp and voutsn, representing input current. v snsc is the voltage between icap and vcap, representing charge current. error for v snsi and v snsc is expressed in v, a conversion to an equivalent current may be made by dividing by the sense resistors, r snsi and r snsc , respectively. typical p er f or m ance c harac t eris t ics supercapacitor backup operation hv electrolytic backup operation shunt operation using v cap2 v in 2v/div v cap 2v/div v out 2v/div 400ms/div back page application circuit 0v 3350 g01 p backup = 25w v in 5v/div v cap 5v/div v out 5v/div 20ms/div application circuit 6 0v 3350 g02 p backup = 25w v cap2 (v) 2.64 current (a) 3 4 5 2.67 2.69 3350 g03 2 1 2.65 2.66 2.68 i cap2 2.70 2.71 0 ?1 i charge v shunt = 2.7v t a = 25c, application circuit 4 unless otherwise noted. ltc 3350 3350fb for more information www.linear.com/ltc3350
8 i in and i charge vs v in i charge vs v cap charger efficiency vs v cap i charge vs v cap i in and i charge vs i out v cap vs vcapfb_dac typical p er f or m ance c harac t eris t ics v cap vs temperature efficiency in boost mode load regulation in boost mode t a = 25c, application circuit 4 unless otherwise noted. v in (v) 11 current (a) 2.9 3.5 36 3350 g04 2.3 1.7 16 21 26 31 i in 4.1 125c 25c ?40c i out = 1a v cap = 6v i charge v cap (v) 0 i charge (a) 2.50 3.75 8 3350 g06 1.25 0 2 4 6 5.00 v in = 12v v in = 24v v in = 35v i in(max) = 2a i out = 1a v cap (v) 0 efficiency (%) 50 75 7.2 3350 g08 25 0 1.8 3.6 5.4 100 v in = 12v v in = 24v v in = 35v i in(max) = 2a i out = 0a v cap (v) 0 i charge (a) 2.50 3.75 8 3350 g05 1.25 0 2 4 6 5.00 v in = 12v v in = 24v v in = 35v i in(max) = 2a i out = 0a i out (a) 0 current (a) 2.50 3.75 3.00 3350 g07 1.25 0 0.75 1.50 2.25 i in 5.00 v in = 12v v in = 24v v in = 35v i in(max) = 2a i charge vcapfb_dac (code) 0 1 2 3 4 5 6 7 8 9 10 11 12 1413 v cap (v) 5.50 6.75 15 3350 g09 4.25 3.00 8.00 i charge = 2a temperature (c) ?40 v cap (v) 7.200 7.205 130 3350 g10 7.195 7.190 7.185 ?6 28 62 96 7.210 capfb_dac = 15 i charge = 2a i out (a) 25 efficiency (%) 50 75 100 10 ?3 10 ?2 10 ?1 10 0 10 1 3350 g11 0 v cap = 2v v cap = 3v v cap = 4v application circuit 5 i out (a) 4.981 v out (boost) (v) 4.988 4.994 5.000 10 ?3 10 ?2 10 ?1 10 0 10 1 3350 g12 4.975 v cap = 2v v cap = 3v v cap = 4v application circuit 5 ltc 3350 3350fb for more information www.linear.com/ltc3350
9 typical p er f or m ance c harac t eris t ics i q vs v in , pulse skipping gpi code vs temperature drv cc current vs boost inductor current intv cc vs charge current intv cc vs temperature t a = 25c, application circuit 4 unless otherwise noted. v in (v) 10 i q (ma) 4.60 4.75 35 3350 g13 4.45 4.30 15 20 25 30 4.90 125c 25c ?40c temperature (c) ?40 code 5470 5475 130 3350 g14 5460 5465 5455 ?6 28 62 96 5480 v gpi = 1v i l (a) 0 i drvcc (ma) 5.0 7.5 6 3350 g15 2.5 0 1.5 3 4.5 10.0 125c 25c ?40c v cap = 4v application circuit 5 i charge (a) 0 intv cc (v) 4.875 4.938 4 3350 g16 4.813 4.750 1 2 3 5.000 v in = 12v 125c 25c ?40c temperature (c) ?40 intv cc (v) 4.875 4.938 130 3350 g17 4.813 4.750 ?6 28 62 96 5.000 ltc 3350 3350fb for more information www.linear.com/ltc3350
10 p in func t ions scl (pin 1): clock pin for the i 2 c/smbus serial port. sda (pin 2): bidirectional data pin for the i 2 c/smbus serial port. smbalert (pin 3): interrupt output. this open-drain output is pulled low when an alarm threshold is exceeded, and will remain low until the acknowledgement of the part s response to an smbus ara. capgd (pin 4): capacitor power good. this open-drain output is pulled low when capfb is below 92% of its regulation point. vc (pin 5): control voltage pin. this is the compensation node for the charge current, input current, supercapacitor stack voltage and output voltage control loops. an rc network is connected between vc and sgnd. nominal voltage range for this pin is 1v to 3v. capfb (pin 6): capacitor stack feedback pin. this pin closes the feedback loop for constant voltage regulation. an external resistor divider between vcap and sgnd with the center tap connected to capfb programs the final supercapacitor stack voltage. this pin is nominally equal to the output of the v cap dac when the synchronous controller is in constant voltage mode while charging. outfb (pin 7): step-up mode feedback pin. this pin closes the feedback loop for voltage regulation of v out during input power failure using the synchronous controller in step-up mode. an external resistor divider between v out and sgnd with the center tap connected to outfb programs the minimum backup supply rail voltage when input power is unavailable. this pin is nominally 1.2 v when in backup and the synchronous controller is not in current limit. to disable step-up mode tie outfb to intv cc . sgnd (pin 8): signal ground. all small-signal and com- pensation components should be connected to this pin, which in turn connects to pgnd at one point. this pin should also kelvin to the bottom plate of the capacitor stack. rt (pin 9): timing resistor. the switching frequency of the synchronous controller is set by placing a resistor, r t , from this pin to sgnd. this resistor is always required. if not present the synchronous controller will not start. gpi (pin 10): general purpose input. the voltage on this pin is digitized directly by the adc. for high impedance inputs an internal buffer can be selected and used to drive the adc. the gpi pin can be connected to a negative temperature coefficient ( ntc) thermistor to monitor the temperature of the supercapacitor stack. a low drift bias resistor is required from intv cc to gpi and a thermistor is required from gpi to ground. connect gpi to sgnd if not used. the digitized voltage on this pin can be read in the meas_gpi register. itst (pin 11): programming pin for capacitance test cur - rent. this current is used to partially discharge the capaci- tor stack at a precise rate for capacitance measurement. this pin servos to 1.2 v during a capacitor measurement. a resistor, r tst , from this pin to sgnd programs the test current. r tst must be at least 121. caprtn (pin 12): capacitor stack shunt return pin. this pin is connected to the grounded bottom plate of the first super capacitor in the stack through a shunt resistor. cap1 (pin 13): first supercapacitor pin. the top plate of the first supercapacitor and the bottom plate of the second supercapacitor are connected to this pin through a shunt resistor. cap1 and caprtn are used to measure the voltage across the first super capacitor and to shunt current around the capacitor to provide balancing and prevent overvoltage. the voltage between this pin and caprtn is digitized and can be read in the meas_ vcap1 register . cap2 ( pin 14): second supercapacitor pin. the top plate of the second supercapacitor and the bottom plate of the third supercapacitor are connected to this pin through a shunt resistor. cap2 and cap1 are used to measure the voltage across the second supercapacitor and to shunt ltc 3350 3350fb for more information www.linear.com/ltc3350
11 p in func t ions current around the capacitor to provide balancing and prevent overvoltage. if not used this pin should be shorted to cap1. the voltage between this pin and cap1 is digitized and can be read in the meas_vcap2 register. cap3 (pin 15): third supercapacitor pin. the top plate of the third supercapacitor and the bottom plate of the fourth supercapacitor are connected to this pin through a shunt resistor. cap3 and cap2 are used to measure the voltage across the third supercapacitor and to shunt current around the capacitor to provide balancing and prevent overvoltage. if not used this pin should be shorted to cap2. the voltage between this pin and cap2 is digitized and can be read in the meas_vcap3 register. cap 4 (pin 16): fourth supercapacitor pin. the top plate of the fourth supercapacitor is connected to this pin through a shunt resistor. cap4 and cap3 are used to measure the voltage on the capacitor and to shunt current around the supercapacitor to provide balancing and prevent overvoltage. if not used this pin should be shorted to cap3. the voltage between this pin and cap3 is digitized and can be read in the meas_vcap4 register. the capacitance test current set by the itst pin is pulled from this pin. cfp ( pin 17): vcapp5 charge pump flying capacitor positive terminal. place a 0.1f between cfp and cfn. cfn (pin 18): vcapp5 charge pump flying capacitor negative terminal. place a 0.1f between cfp and cfn. vcapp 5 (pin 19): charge pump output. the internal charge pump drives this pin to vcap + intv cc which is used as the high side rail for the outfet gate drive and charge current sense amplifier. connect a 0.1 f capacitor from vcapp5 to vcap. outfet (pin 20): output ideal diode gate drive out - put. this pin controls the gate of an external n-channel mosfet used as an ideal diode between v out and v cap . the gate drive receives power from the internal charge pump output vcapp5. the source of the n- channel mosfet should b e connected to vcap and the drain should be connected to voutsn. if the output ideal diode mosfet is not used, outfet should be left floating. vcap (pin 21): supercapacitor stack voltage and charge current sense amplifier negative input. connect this pin to the top of the supercapacitor stack. the voltage at this pin is digitized and can be read in the meas_ vcap register. icap (pin 22): charge current sense amplifier positive input. the icap and vcap pins measure the voltage across the sense resistor, r snsc , to provide instantaneous cur- rent signals for the control loops and esr measurement system . the maximum charge current is 32mv/r snsc . vcc2p 5 (pin 23): internal 2.5 v regulator output. this regulator provides power to the internal logic circuitry. decouple this pin to ground with a minimum 1 f low esr tantalum or ceramic capacitor. sw (pin 24): switch node connection to the inductor. the negative terminal of the boot-strap capacitor, c b , is connected to this pin. the voltage on this pin is also used as the source reference for the top side n-channel mos - fet gate drive. in step-down mode, the voltage swing on this pin is from a diode ( external) forward voltage below ground to v out . in step-up mode the voltage swing is from ground to a diode forward voltage above v out . tgate (pin 25): top gate driver output. this pin is the output of a floating gate driver for the top external n - ch annel mosfet. the voltage swing at this pin is ground to v out + drv cc . bst (pin 26): tgate driver supply input. the positive terminal of the boot-strap capacitor, c b , is connected to this pin. this pin swings from a diode voltage drop below drv cc up to v out + drv cc . bgate (pin 27): bottom gate driver output. this pin drives the bottom external n-channel mosfet between pgnd and drv cc . drv cc (pin 28): power rail for bottom gate driver. con- nect to intv cc or to an external supply. decouple this pin to ground with a minimum 2.2 f low esr tantalum or ceramic capacitor. do not exceed 5.5v on this pin. ltc 3350 3350fb for more information www.linear.com/ltc3350
12 p in func t ions intv cc (pin 29): internal 5 v regulator output. the control circuits and gate drivers ( when connected to drv cc ) are powered from this supply. if not connected to drv cc , decouple this pin to ground with a minimum 1 f low esr tantalum or ceramic capacitor. voutsn (pin 30): input current limiting amplifier nega - tive input . a sense resistor, r snsi , between voutsp and voutsn sets the input current limit. the maximum input current is 32mv/r snsi . an rc network across the sense resistor can be used to modify loop compensation. to disable input current limit, connect this pin to voutsp. voutsp (pin 31): backup system supply voltage and input current limiting amplifier positive input. the voltage across the voutsp and voutsn pins are used to regulate input current. this pin also serves as the power supply for the ic. the voltage at this pin is digitized and can be read in the meas_vout register. voutm5 (pin 32): v out C 5 v regulator. this pin is regu- lated to 5 v below v out or to ground if v out < 5 v. this rail provides power to the input current sense amplifier. decouple this pin with at least 1f to v out . infet (pin 33): input ideal diode gate drive output. this pin controls the gate of an external n-channel mosfet used as an ideal diode between v in and v out . the gate drive receives power from an internal charge pump. the source of the n-channel mosfet should be connected to v in and the drain should be connected to voutsp. if the input ideal diode mosfet is not used, infet should be left floating. v in ( pin 34): external dc power source input. decouple this pin with at least 0.1 f to ground. the voltage at this pin is digitized and can be read in the meas_vin register. cap_slct0, cap_slct 1 ( pins 35, 36): cap_slct0 and cap_slct1 set the number of super-capacitors used. refer to table 1 in the applications information section. pfi (pin 37): power-fail comparator input. when the voltage at this pin drops below 1.17v, pfo is pulled low and step-up mode is enabled. pfo (pin 38): power-fail status output. this open-drain output is pulled low when a power fault has occurred. pgnd ( exposed pad pin 39): power ground. the exposed pad must be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the ltc3350 for rated thermal performance . it must be tied to the sgnd pin. ltc 3350 3350fb for more information www.linear.com/ltc3350
13 b lock diagra m + ? + ? + ? 30mv 30mv intv cc v ref vcapfb_dac[3:0] vcapfb_dac vcapfb_dac v in capfb outfb vc rt intv cc infet voutsp voutm5 voutsn + ? x37.5 + ? x37.5 i in i chg 5v ldo ?5v ldo d/a a/d v ref intv cc intv cc + ? v ref + ? v ref v outsp i ref + ? + ? outfet cfm vcapp5 cfp vcap icap bst tgate sw + ? charge pump drv cc bgate cap4 bidirectional switching controller logic vcc2p5 i in ichg vcap v out v in cap4 cap3 cap2 cap1 caprtn dtemp capgd pfi gpi sgnd bandgap v ref osc 2.5v ldo shunt controller cap3 balancer shunt controller cap2 balancer shunt controller cap1 balancer shunt controller caprtn itst balancer pfo + ? v ref 3350 bd gpibuf + ? v ref capfb multiplexer + ? cap_slct0 cap_slct1 smbalert sda scl + ? 34 33 31 32 30 20 17 18 19 21 22 26 25 24 28 27 16 15 14 13 12 11 10 8 pgnd 39 1 2 3 36 35 38 37 4 23 29 9 5 7 6 ltc 3350 3350fb for more information www.linear.com/ltc3350
14 o pera t ion ti m ing diagra m introduction the ltc3350 is a highly integrated backup power controller and system monitor. it features a bidirectional switching controller, input and output ideal diodes, supercapacitor shunts/balancers, a power-fail comparator, a 14-bit adc and i 2 c/smbus programmability with status reporting. if v in is above an externally programmable pfi threshold voltage, the synchronous controller operates in step- down mode and charges a stack of supercapacitors. a program - mable input current limit ensures that the supercapacitors will automatically be charged at the highest possible charge current that the input can support. if v in is below the pfi threshold, then the synchronous controller will run in reverse as a step-up converter to deliver power from the supercapacitor stack to v out . the two ideal diode controllers drive external mosfets to provide low loss power paths from v in and v cap to v out . the ideal diodes work seamlessly with the bidirectional controller to provide power from the supercapacitors to v out without backdriving v in . the ltc3350 provides balancing and overvoltage protec- tion to a series stack of one to four supercapacitors. the internal capacitor voltage balancers eliminate the need for external balance resistors. overvoltage protection is provided by shunt regulators that use an internal switch and an external resistor across each super capacitor. the ltc3350 monitors system voltages, currents, and die temperature. a general purpose input ( gpi) pin is provided to measure an additional system parameter or implement a thermistor measurement. in addition, the ltc3350 can measure the capacitance and resistance of the supercapacitor stack. this provides indication of the health of the supercapacitors and, along with the v cap voltage measurement, provides information on the total energy stored and the maximum power that can be delivered. bidirectional switching controllerstep-down mode the bidirectional switching controller is designed to charge a series stack of supercapacitors ( figure 1). charging proceeds at a constant current until the supercapacitors reach their maximum charge voltage determined by the capfb servo voltage and the resistor divider between v cap and capfb. the maximum charge current is determined by the value of the sense resistor, r snsc , used in series with the inductor. the charge current loop servos the voltage across the sense resistor to 32 mv. when charging begins, an internal soft-start ramp will increase the charge current from zero to full current in 2 ms. the v cap voltage and charge current can be read from the meas_vcap and meas_ichrg registers, respectively. sda scl s sr p s t hd(sda) s = start, sr = repeated start, p = stop t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 3350 td definition of timing for f/s mode devices on the i 2 c bus ltc 3350 3350fb for more information www.linear.com/ltc3350
15 o pera t ion + + + + + ? + ? + ? 30mv input current controller charge current controller bidirectional switching controller step-down mode v ref i in v in v in ltc3350 infet voutsp voutsn v out (to system) tgate i chg bgate icap vcap r snsc r snsi 3350 f01 + ? i ref v ref capacitor voltage controller + ? + ? capfb vc 37.5 d/a vcapfb_dac[3:0] + ? figure 1. power path block diagrampower available from v in the ltc3350 provides constant power charging ( for a fixed v in ) by limiting the input current drawn by the switching controller in step-down mode. the input current limit will reduce charge current to limit the voltage across the input sense resistor, r snsi , to 32 mv. if the combined system load plus supercapacitor charge current is large enough to cause the switching controller to reach the programmed input current limit, the input current limit loop will reduce the charge current by precisely the amount necessary to enable the external load to be satisfied. even if the charge current is programmed to exceed the allowable input current, the input current will not be violated; the supercapacitor charger will reduce its current as needed. note that the parts quiescent and gate drive currents are not included in the input current measurement.the input current can be read from the meas_iin register. bidirectional switching controllerstep-up mode the bidirectional switching controller acts as a step-up converter to provide power from the supercapacitors to v out when input power is unavailable ( figure 2). the pfi comparator enables step-up mode. v out regulation is set by a resistor divider between v out and outfb. to disable step-up mode tie outfb to intv cc . step-up mode can be used in conjunction with the output ideal diode. the v out regulation voltage can be set below the capacitor stack voltage. upon removal of input power, power to v out will be provided from the supercapacitor stack via the output ideal diode. v cap and v out will fall as the load current discharges the supercapacitor stack. the output ideal diode will shut off when the voltage on outfb falls below 1.3 v and v out will fall a pn diode (~700mv) below v cap . if outfb falls below 1.2 v when the output ltc 3350 3350fb for more information www.linear.com/ltc3350
16 o pera t ion + + + + + ? + ? 30mv output voltage controller bidirectional switching controller step-up mode v ref ltc3350 voutsn v out (to system) v cap > v out v cap < v out tgate outfet outfb bgate icap vcap r snsc 3350 f02 vc + ? figure 2. power path block diagrampower backup ideal diode shuts off, the synchronous controller will turn on immediately. if outfb is above 1.2 v when the output ideal diode shuts off, the load current will flow through the body diode of the output ideal diode n- channel mosfet for a period of time until outfb falls to 1.2 v. the synchronous controller will regulate outfb to 1.2 v when it turns on , holding up v out while the supercapacitors discharge to ground. the synchronous controller in step- up mode will run nonsynchronously when v cap is less than 100 mv below v out . it will run synchronously when v cap falls 200mv below v out . ideal diodes the ltc3350 has two ideal diode controllers that drive external n-channel mosfets. the ideal diodes consist of a precision amplifier that drives the gates of n-channel mosfets whenever the voltage at v out is approximately 30mv (v fwd ) below the voltage at v in or v cap . within the amplifiers linear range, the small-signal resistance of the ideal diode will be quite low, keeping the forward drop near 30 mv. at higher current levels, the mosfets will be in full conduction. the input ideal diode prevents the supercapacitors from back driving v in during backup mode. a fast-off com- parator shuts off the n-channel mosfet if v in falls 30mv below v out . the pfi comparator also shuts off the mosfet during power failure. the output ideal diode provides a path for the supercapaci - tors to power v out when v in is unavailable. in addition to a fast-off comparator, the output ideal diode also has a fast- on comparator that turns on the external mosfet when v out drops 65 mv below v cap . the output ideal diode will shut off when outfb is just above regulation allowing the synchronous controller to power v out in step-up mode. ltc 3350 3350fb for more information www.linear.com/ltc3350
17 o pera t ion gate drive supply ( drv cc ) the bottom gate driver is powered from the drv cc pin. it is normally connected to the intv cc pin. an external ldo can also be used to power the gate drivers to minimize power dissipation inside the ic. see the applications information section for details. undervoltage lockout (uvlo) internal undervoltage lockout circuits monitor both the intv cc and drv cc pins. the switching controller is kept off until intv cc rises above 4.3 v and drv cc rises above 4.2v. hysteresis on the uvlos turn off the controller if either intv cc falls below 4v or drv cc falls below 3.9v. charging is not enabled until voutsn is 185 mv above the supercapacitor voltage and v in is above the pfi threshold. charging is disabled when voutsn falls to within 90 mv of the supercapacitor voltage or v in is below the pfi threshold. rt oscillator and switching frequency the rt pin is used to program the switching frequency. a resistor, r t , from this pin to ground sets the switching frequency according to: f sw mhz ( ) = 53.5 r t k ? ( ) r t also sets the scale factor for the capacitor measurement value reported in the meas_cap register, described in the capacitance and esr measurement section of this data sheet. input overvoltage protection the ltc3350 has overvoltage protection on its input. if v in exceeds 38.6 v, the switching controller will hold both switches off. the controller will resume switching if v in falls below 37.2v. v cap dac the feedback reference for the capfb servo point can be programmed using an internal 4- bit digital - to - analog converter ( dac). the reference voltage can be programmed from 0.6375 v to 1.2 v in 37.5mv increments. the dac defaults to full scale (1.2v ) and is programmed via the vcapfb_ dac register. supercapacitors lose capacitance as they age. by initially setting the v cap dac to a low setting, the final charge voltage on the supercapacitors can be increased as they age to maintain a constant level of stored backup energy throughout the lifetime of the supercapacitors. power-fail (pf) comparator the ltc3350 contains a fast power-fail ( pf) comparator which switches the part from charging to backup mode in the event the input voltage, v in , falls below an externally programmed threshold voltage. in backup mode, the input ideal diode shuts off and the supercapacitors power the load either directly through the output ideal diode or through the synchronous controller in step-up mode. the pf comparator threshold voltage is programmed by an external resistor divider via the pfi pin. the output of the pf comparator also drives the gate of an open-drain nmos transistor to report the status via the pfo pin. when input power is available the pfo pin is high impedance. when v in falls below the pf comparator threshold, pfo is pulled down to ground. the output of the pf comparator may also be read from the chrg_pfo bit in the chrg_status register. charge status indication the ltc3350 includes a comparator to report the status of the supercapacitors via an open-drain nmos transistor on the capgd pin. this pin is pulled to ground until the capfb pin voltage rises to within 8% of the v cap dac setting. once the capfb pin is above this threshold, the capgd pin goes high impedance. the output of this comparator may also be read from the chrg_cappg bit in the chrg_status register. capacitor voltage balancer the ltc3350 has an integrated active stack balancer. this balancer slowly balances all of the capacitor voltages to within about 10 mv of each other. this maximizes the life of the supercapacitors by keeping the voltage on each as low as possible to achieve the needed total stack voltage. when the difference between any two capacitor volt - ages exceeds about 10 mv, the capacitor with the largest ltc 3350 3350fb for more information www.linear.com/ltc3350
18 o pera t ion voltage is discharged with a resistive balancer at about 10ma until all capacitor voltages are within 10mv. capacitor shunt regulators in addition to balancing, there is a need to protect each capacitor from overvoltage during charging. the capacitors in the stack will not have exactly the same capacitance due to manufacturing tolerances or uneven aging. this will cause the capacitor voltages to increase at different rates with the same charge current. if this mismatch is severe enough or if the capacitors are being charged to near their maximum voltage, it becomes necessary to limit the volt - age increase on some capacitors while still charging the other capacitors. up to 500 ma of current may be shunted around a capacitor whose voltage is approaching the pro - grammable shunt voltage. this shunt current reduces the charge rate of that capacitor relative to the other capacitors. if a capacitor continues to approach its shunt voltage, the charge current is reduced. this protects the capacitor from overvoltage while still charging the other capacitors, although at a reduced rate of charge. the shunt voltage is programmable in the vshunt register. shunt voltages up to 3.6 v may be programmed in 183.5 v increments. the shunt regulators can be disabled by programming vshunt to zero (0 x0000). the default value is 0 x3999, resulting in a shunt voltage of 2.7v. i 2 c/smbus and smbalert the ltc3350 contains an i 2 c/ smbus port. this port allows communication with the ltc3350 for configuration and reading back telemetry data. the port supports two smbus formats, read word and write word. refer to the smbus specification for details of these formats. the registers accessible via this port are organized on an 8- bit address bus and each register is 16 bits wide. the command code (or sub-address) of the smbus read/write word formats is the 8- bit address of each of these registers. the address of the ltc3350 is 0b0001001. the smbalert pin is asserted ( pulled low) whenever an enabled limit is exceeded or when an enabled status event happens ( see limit check and alarms and monitor status register). the ltc3350 will deassert the smbalert pin only after responding to an smbus alert response address ( ara), an smbus protocol used to respond to a smbalert. the host will read from the ara (0b0001100) and each part asserting smbalert will begin to respond with its address. the responding parts arbitrate in such a way that only the part with the lowest address responds. only when a part has responded with its address does it release the smbalert signal. if multiple parts are as - serting the smbalert signal then multiple reads from the ara are needed. for more information refer to the smbus specification. details on the registers accessible through this interface are available in the register map and register descriptions sections of this data sheet. analog-to-digital converter the ltc3350 has an integrated 14- bit sigma-delta analog- to-digital converter ( adc). this converter is automatically multiplexed between all of the measured channels and its results are stored in registers accessible via the i 2 c/ smbus port. there are 11 channels measured by the adc, each of which takes approximately 1.6 ms to measure. in addition to providing status information about the system voltages and currents, some of these measurements are used by the ltc3350 to balance, protect, and measure the capacitors in the stack. the result of the analog-to-digital conversion is stored in a 16- bit register as a signed, twos complement number. the lower two bits of this number are sub-bits. these bits are adc outputs which are too noisy to be reliably used on any single conversion, however, they may be included if multiple samples are averaged. the measurements from the adc are directly stored in the meas_vcap1, meas_vcap2, meas_vcap3, meas_vcap4, meas_gpi, meas_vin, meas_vcap, meas_vout, meas_iin, meas_ichg and meas_dtemp registers. capacitance and esr measurement the ltc3350 has the ability to measure the capacitance and equivalent series resistance ( esr) of its supercapacitor stack. this measurement is performed with minimal impact to the system, and can be done while the supercapacitor backup system is online. this measurement discharges ltc 3350 3350fb for more information www.linear.com/ltc3350
19 o pera t ion the capacitor stack by a small amount (200 mv). if input power fails during this test, the part will go into backup mode and the test will terminate. the capacitance test is performed only once the supercapacitors have finished charging. the test temporarily disables the charger, then discharges the supercapacitors by 200mv with a precision current. the discharge time is measured and used to calculate the capacitance with the result of this measurement stored in the meas_cap register. the number reported is proportional to the capacitance of the entire stack. two different scales can be set using the ctl_cap_scale bit in the ctl_reg register. if ctl_cap_scale is set to 0 ( for large value capacitor stacks), use the following equation to convert the meas_cap value to farads: c stack = r t r tst ? 336f ? meas _ cap if ctl _ cap _ scale is set to 1 ( for small value capactor stacks), use the following equation to convert the meas_cap value to farads: c stack = r t r tst ? 3.36f ? meas _ cap in the two previous equations r t is the resistor on the rt pin and r tst is the resistor on the itst pin. the esr test is performed immediately following the capacitance test. the switching controller is switched on and off several times. the changes in charge current and stack voltage are measured. these measurements are used to calculate the esr relative to the charge current sense resistor. the result of this measurement is stored in the meas_esr register. the value reported in meas_esr can be converted to ohms using the following equation: r esr = r snsc 64 ? meas _ esr where r snsc is the charge current sense resistor in series with the inductor. the capacitance and capacitor esr measurements do not automatically run as the other measurements do. they must be initiated by setting the ctl_strt_capesr bit in the ctl_reg register. this bit will automatically clear once the measurement begins. if the cap_esr_per register is set to a non-zero value, the measurement will be repeated after the time programmed in the cap_esr_per register. each lsb in the cap_esr_per register represents 10 seconds. the capacitance and esr measurements may fail to complete for several reasons, in which case the respective mon_cap_failed or mon_esr_failed bit will be set. the capacitance test may fail due to a power failure or if the 200mv discharge trips the capgd comparator. the esr test will also fail if the capacitance test fails. the esr test uses the charger to supply a current and then measures the supercapacitor stack voltage with and without that cur - rent. if the esr is greater than 1024 times r snsc , the esr measurement will fail. the esr measurement is adaptive; it uses knowledge of the esr from previous measure- ments to program the test current. the capacitance and esr tests should initially be run several times when first powering up to get the most accuracy out of the system. it is possible for the first few measurements to give low quality results or fail to complete and after running several times will complete with a quality result. monitor status register the ltc3350 has a monitor status register (mon_status) which contains status bits indicating the state of the ca - pacitance and esr monitoring system. these bits are set and cleared by the capacitor monitor upon certain events during a capacitor and esr measurement, as described in the capacitance and esr measurement section. there is a corresponding msk_ mon_ status register. writing a one to any of these bits will cause the smbalert pin to pull low when the corresponding bit in the msk_mon_sta - tus register has a rising edge. this allows reduced polling of the ltc3350 when waiting for a capacitance or esr measurement to complete. details of the mon_status and msk_mon_status registers can be found in the register descriptions section of this data sheet. ltc 3350 3350fb for more information www.linear.com/ltc3350
20 o pera t ion charge status register the ltc3350 charger status register ( chrg_ status) contains data about the state of the charger, switcher, shunts, and balancers. details of this register may be found in the register description sections of this data sheet. limit checking and alarms the ltc3350 has a limit checking function that will check each measured value against i 2 c/smbus programmable limits. this feature is optional, and all the limits are dis- abled by default. the limit checking is designed to simplify system monitoring, eliminating the need to continuously poll the ltc3350 for measurement data. if a measured parameter goes outside of the programmed level of an enabled limit, the associated bit in the alarm_reg register is set high and the smbalert pin is pulled low. this informs the i 2 c/ smbus host a limit has been exceeded. the alarms register may then be read to determine exactly which programmed limits have been exceeded. a single adc is shared between the 11 channels with about 18ms between consecutive measurements of the same channel. in a transient condition, it is possible for these parameters to exceed their programmed levels in between consecutive adc measurements without setting the alarm. once the ltc 3350 has responded to an smbus ara the smbalert pin is released. the part will not pull the pin low again until another limit is exceeded. to reset a limit that has been exceeded, it must be cleared by writing a one to the respective bit in the clr_alarms register. a number of the ltc3350s registers are used for limit checking. individual limits are enabled or disabled in the msk_alarms registers. once an enabled alarms measured value exceeds the programmed level for that alarm the alarm is set. that alarm may only be cleared by writing a one to the appropriate bit of the clr_alarms register. all alarms that have been set and have not yet been cleared may be read in the alarm_reg register. all of the individual measured voltages have a corresponding undervoltage ( uv) and overvoltage ( ov) alarm level. all of the individual capacitor voltages are compared to the same alarm levels, set in the cap _ ov _ lvl and cap _ uv _ lvl registers . the input current measurement has an overcurrent (oc) alarm programmed in the iin_oc_lvl register. the charge current has an undercurrent alarm programmed in the ichg_uc_lvl register. die t emperature sensor the ltc3350 has an integrated die temperature sensor monitored by the adc and digitized to the meas_dtemp register. an alarm may be set on die temperature by setting the dtemp_ cold_ lvl and/ or dtemp_ hot_ lvl registers and enabling their respective alarms in the msk_alarms register. to convert the code in the meas_dtemp register to degrees celsius use the following: t die (c) = 0.028 ? meas_dtemp C 251.4 general purpose input the general purpose input ( gpi) pin can be used to measure an additional system parameter. the voltage on this pin is directly digitized by the adc. for high impedance inputs, an internal buffer may be selected and used to drive the adc. this buffer is enabled by setting the ctl_ gpi_ buffer_ en bit in the ctl_reg register. with this buffer, the input range is limited from 0 v to 3.5 v. if this buffer is not used, the range is from 0 v to 5 v, however, the input stage of the adc will draw about 0.4 a per volt from this pin. the adc input is a switched capacitor amplifier running at about 1mhz, so this current draw will be at that frequency. the pin current can be eliminated at the cost of reduced range and increased offset by enabling the buffer. alarms are available for this pin voltage with levels programmed using the gpi_ uv_ lvl and gpi_ ov_ lvl registers. these alarms are enabled using the msk_gpi_uv and msk_gpi_ov bits in the msk_alarms register. to monitor the temperature of the supercapacitor stack, the gpi pin can be connected to a negative temperature coefficient ( ntc) thermistor. a low drift bias resistor is required from intv cc to gpi and a thermistor is required from gpi to ground. connect gpi to sgnd if not used. ltc 3350 3350fb for more information www.linear.com/ltc3350
21 a pplica t ions i n f or m a t ion digital configuration although the ltc3350 has extensive digital features, only a few are required for basic use. the shunt voltage should be programmed via the vshunt register if a value other than the default 2.7 v is required. the capacitor voltage feedback reference defaults to 1.2 v; it may be changed in the vcapfb_dac register. all other digital features are optional and used for moni- toring. the adc automatically runs and stores conver- sions to registers ( e.g., meas_vcap). capacitance and esr measurements only run if requested, however, they may be scheduled to repeat if desired ( ctl_strt_capesr and cap_ esr_per). each measured parameter has programmable limits ( e.g., vcap_uv_lvl and vcap_ov_lvl) which may trigger an alarm and smbalert when enabled. these alarms are disabled by default. capacitor configuration the ltc3350 may be used with one to four supercapaci- tors. if less than four capacitors are used, the capacitors must be populated from caprtn to cap4, and the unused cap pins must be tied to the highest used cap pin. for example, if three capacitors are used, cap4 should be tied to cap3. if only two capacitors are used, both cap4 and cap 3 should be tied to cap2. the number of capacitors used must be programmed on the cap_ slct0 and cap_slct1 pins by tying the pins to vcc2p5 for a one and ground for a zero as shown in table 1. the value programmed on these pins may be read back from the num_caps register via i 2 c/smbus. table 1 cap_slct1 cap_slct0 num_caps register value number of cap acitors 0 0 0 1 0 1 1 2 1 0 2 3 1 1 3 4 capacitor shunt regulator programming v shunt is programmed via the i 2 c/smbus interface and defaults to 2.7 v at initial power-up. v shunt serves to limit the voltage on any individual capacitor by turning on a shunt around that capacitor as the voltage approaches v shunt . caprtn, cap1, cap2, cap3 and cap4 must be connected to the supercapacitors through resistors which serve as ballasts for the internal shunts. the shunt cur - rent is approximately v shunt divided by twice the shunt resistance value. for a v shunt of 2.7v, 2.7 resistors should be used for 500 ma of shunt current. the shunts have a duty cycle of up to 75%. the power dissipated in a single shunt resistor is approximately: p shunt 3v shunt 2 16r shunt and the resistors should be sized accordingly. if the shunts are disabled, make r shunt 100. since the shunt current is less than what the switcher can supply, the on-chip logic will automatically reduce the charging current to allow the shunt to protect the capacitor . this greatly reduces the charge rate once any one shunt is activated. for this reason, v shunt should be programmed as high as possible to reduce the likelihood of it activating during a charge cycle. ideally, v shunt would be set high enough so that any likely capacitor mismatches would not cause the shunts to turn on. this keeps the charger operat - ing at the highest possible charge current and reduces the charge time. if the shunts never turn on, the charge cycle completes quickly and the balancers eventually equalize the voltage on the capacitors. the shunt setting may also be used to discharge the capacitors for testing, storage or other purposes. setting input and charge currents the maximum input current is determined by the resis - tance across the voutsp and voutsn pins, r snsi . the maximum charge current is determined by the value of the sense resistor, r snsc , used in series with the induc- tor. the input and charge current loops servo the voltage across their respective sense resistor to 32 mv. therefore, the maximum input and charge currents are: i in(max) = 32mv r snsi i chg(max) = 32mv r snsc ltc 3350 3350fb for more information www.linear.com/ltc3350
22 a pplica t ions i n f or m a t ion the peak inductor current limit, i peak , is 80% higher than the maximum charge current and is equal to: i peak = 58mv r snsc note that the input current limit does not include the parts quiescent and gate drive currents. the total current drawn by the part will be i in(max) + i q + i g , where i q is the non- switching quiescent current and i g is the gate drive current. low current charging and high current backup the ltc3350 can accommodate applications requiring low charge currents and high backup currents. in these applications, program the desired charge current using r snsi . the higher current needed during backup can be set using r snsc . the input current limit will override the charge current limit when the supercapacitors are charging while the charge current limit provides sufficient current capability for backup operation. the charge current will be limited to i chg(max) at low v cap ( i.e., low duty cycles). as v cap rises, the switching controllers input current will increase until it reaches i in(max) . the input current will be maintained at i in(max) and the charge current will decrease as v cap rises further. some applications may want to use only a portion of the input current limit to charge the supercapacitors. tw o input current sense resistors placed in series can be used to accomplish this as shown in figure 3. voutsp is kelvin connected to the positive terminal of r snsi1 and voutsn is kelvin connected to the negative terminal of r snsi2 . the load current is pulled across r snsi1 while the input current to the charger is pulled across r snsi1 and r snsi2 . the input current limit is: 32 mv = r snsi1 ? i load + (r snsi1 + r snsi2 ) ? i inchg for example, suppose that only 2 a of input current is de- sired to c harge th e supercapacitors but the system load and charger combined can pull a total of up to 4 a from the supply. setting r snsi1 = r snsi2 = 8 m will set a 4 a cur- rent limit for the load + charger while setting a 2 a limit for the charger. with no system load, the charger can pull up to 2 a of input current. as the load pulls 0 a to 4 a of current the charger s input current will reduce from 2 a down to 0 a. the following equation can be used to determine charging input current as a function of system load current: i inchg = 32mv r snsi1 + r snsi2 C r snsi1 r snsi1 + r snsi2 ? i load the contact resistance of the negative terminal of r snsi 1 and the positive terminal of r snsi2 as well as the resistance of the trace connecting them will cause variability in the input current limit. to minimize the error, place both input current sense resistors close together with a large pcb pad area between them as the system load current is pulled from the trace connecting the two sense resistors. note that the backup current will flow through r snsi2 . the r snsi2 package should be sized accordingly to handle the power dissipation. figure 3 v in v in infet voutsp r snsi1 r snsi2 ltc3350 voutsn i inchg i load v out (to system) tgate bgate 3350 f03 setting v cap voltage the ltc3350 v cap voltage is set by an external feedback resistor divider, as shown in figure 4. the regulated output voltage is determined by: v cap = 1 + r fbc1 r fbc2 ? ? ? ? ? ? capfbref where capfbref is the output of the v cap dac, pro- grammed in the vcapfb_dac register. great care should be taken to route the capfb line away from noise sources, such as the sw line. power-fail comparator input voltage threshold the input voltage threshold below which the power-fail status pin, pfo , indicates a power-fail condition and the ltc 3350 3350fb for more information www.linear.com/ltc3350
23 a pplica t ions i n f or m a t ion ltc3350 bidirectional controller switches to step - up mode is programmed using a resistor divider from the v in pin to sgnd via the pfi pin such that: v in = 1 + r pf1 r pf2 ? ? ? ? ? ? v pfi(th) where v pfi(th) is 1.17 v. typical values for r pf1 and r pf2 are in the range of 40k to 1m. see figure 5. the input voltage above which the power-fail status pin pfo is high impedance and the bidirectional controller switches to step-down mode is: v in = 1 + r pf1 r pf2 ? ? ? ? ? ? v pfi(th) + v pfi(hys) ( ) where v pfi(hys) is the hysteresis of the pfi comparator and is equal to 30mv. mn1 and mp1 can be implemented with a single pack- age n - channel and p-channel mosfet pair such as the si1555dl or si1016cx. the drain leakage current of mn1, when its gate voltage is at ground, can introduce an offset in the threshold. to minimize the effect of this leakage cur - rent r pf1 , r pf2 and r pf3 should be between 1 k and 100k. setting v out voltage in backup mode the output voltage for the controller in step-up mode is set by an external feedback resistor divider, as shown in figure 7. the regulated output voltage is determined by: v out = 1 + r fbo1 r fbo2 ? ? ? ? ? ? 1.2v great care should be taken to route the outfb line away from noise sources, such as the sw line. figure 7. v out voltage divider and compensation network figure 4. v cap voltage feedback divider ltc3350 capfb v cap r fbc1 r fbc2 3350 f04 ltc3350 pfi v in r pf1 r pf2 3350 f05 figure 5. pfi threshold voltage divider figure 6. pfi threshold divider with added hystersis additional hysteresis can be added by switching in an additional resistor, r pf3 , in parallel with r pf2 when the voltage at pfi falls below 1.17 v as shown in figure 6. the falling v in threshold is the same as before but the rising v in threshold becomes: v in = 1 + r pf1 r rp2 + r pf1 r pf3 ? ? ? ? ? ? v pfi(th) + v pfi(hyst) ( ) vc outfb ltc3350 v ref r c (opt) r fbo1 r fbo2 r fo (opt) c fo (opt) c fbo1 v out c c + ? 3350 f07 ltc3350 pfi v dd pfo v in r pf1 r pf2 r pf3 mp1 mn1 3350 f06 ltc 3350 3350fb for more information www.linear.com/ltc3350
24 a pplica t ions i n f or m a t ion compensation the input current, charge current, v cap voltage, and v out voltage loops all require a 1 nf to 10 nf capacitor from the vc node to ground. when using the output ideal diode and backing up to low voltages (<8 v) use 8.2 nf to 10 nf on vc. when not using the output ideal diode 4.7 nf to 10nf on vc is recommended. for very high backup voltages (>15v) 1nf to 4.7nf is recommended. in addition to the vc node capacitor, the v out voltage loop requires a phase-lead capacitor, c fbo1 , for stability and improved transient response during input power failure (figure 7). the product of the top divider resistor and the phase-lead capacitor should be used to create a zero at approximately 2khz: r fbo1 ? c fbo1 1 2 2khz ( ) choose an r fbo1 such that c fbo1 is 100 pf to minimize the effects of parasitic pin capacitance. because the phase- lead capacitor introduces a larger ripple at the input of the v out transconductance amplifier, an additional rc lowpass filter from the v out divider to the outfb pin may be needed to eliminate voltage ripple spikes. the filter time constant should be located at the switching frequency of the synchronous controller: r fo ? c fo = 1 2 f sw with c fo > 10pf to minimize the effects of parasitic pin capacitance. for back up applications where the v out regulation voltage is low (~5 v to 6 v), an additional 1 k to 3k resistor, r c , in series with the vc capacitor can improve stability and transient response. minimum v cap voltage in backup mode in backup mode, power is provided to the output from the supercapacitors either through the output ideal diode or the synchronous controller operating in step-up mode. the output ideal diode provides a low loss power path from the supercapacitors to v out . the minimum internal (open-circuit) supercapacitor voltage will be equal to the minimum v out necessary for the system to operate plus the voltage drops due to the output ideal diode and equivalent series resistance, r sc , of each supercapacitor in the stack. example: system needs 5 v to run and draws 1 a during backup. there are four supercapacitors in the stack, each with an r sc of 45 m. the output ideal diode forward regulation voltage is 30mv ( outfet r ds(on) < 30m). the minimum open-circuit supercapacitor voltage is: v cap(min) = 5v + 0.030v + (1a ? 4 ? 45m) = 5.21v using the synchronous controller in step-up mode allows the supercapacitors to be discharged to a voltage much lower than the minimum v out needed to run the system. the amount of power that the supercapacitor stack can deliver at its minimum internal ( open - circuit) voltage should be greater than what is needed to power the output and the step-up converter. according to the maximum power transfer rule: p cap(min) = v cap(min) 2 4 ? n ? r sc > p backup in the equation above is the efficiency of the synchro- nous controller in step-up mode and n is the number of supercapacitors in the stack. example: system needs 5 v to run and draws 1 a during backup. there are four supercapacitors in the stack ( n?=?4), each with an r sc of 45 m. the converter efficiency is 90%. the minimum open- circuit supercapacitor voltage is: v cap(min) = 4 ? 4 ? 45m ? ? 5v ? 1a 0.9 = 2.0v in this case, the voltage seen at the terminals of the ca- pacitor stack is half this voltage, or 1 v, according to the maximum power transfer rule. ltc 3350 3350fb for more information www.linear.com/ltc3350
25 a pplica t ions i n f or m a t ion note the minimum v cap voltage can also be limited by the peak inductor current limit (180% of maximum charge cur - rent) and the maximum duty cycle in step- up mode (~90%). optimizing supercapacitor energy storage capacity in most systems the supercapacitors will provide backup power to one or more dc/ dc converters. a dc/ dc converter presents a constant power load to the supercapacitor. when the supercapacitors are near their maximum voltage, the loads will draw little current. as the capacitors discharge, the current drawn from supercapacitors will increase to maintain constant power to the load. the amount of energy required in back up mode is the product of this constant backup power, p backup , and the backup time, t backup . the energy stored in a stack of n supercapacitors available for backup is: 1 2 nc sc cell(max) 2 v C cell(min) 2 v ( ) where c sc , v cell(max) and v cell(min) are the capacitance, maximum voltage and minimum voltage of a single ca- pacitor in the stack, respectively. the maximum voltage on the stack is v cap(max) = n ? v cell(max) . the minimum voltage on the stack is v cap(min) = n ? v cell(min) . some of this energy will be dissipated as conduction loss in the esr of the supercapacitor stack. a higher backup power requirement leads to a higher conduction loss for a given stack esr. the amount of capacitance needed can be found by solving the following equation for c sc : p backup ? t backup = 1 4 nc sc max ? cell(max) 2 v C min ? cell(min) 2 v C 4r sc ? p backup n ln max ? v cell(max) min ? v cell(min) ? ? ? ? ? ? ? ? ? ? ? ? ? ? where: max = 1 + 1C 4r sc ? p backup n cell(max) 2 v and, min = 1 + 1C 4r sc ? p backup n cell(min) 2 v r sc is the equivalent series resistance ( esr) of a single supercapacitor in the stack. note that the maximum power transfer rule limits the minimum cell voltage to: v cell(min) = v cap(min) n 4r sc ? p backup n to minimize the size of the capacitance for a given amount of backup energy, the maximum voltage on the stack, v cell(max) , can be increased. however, the voltage is limited to a maximum of 2.7 v and this may lead to an unacceptably low capacitor lifetime. an alternative option would be to keep v cell(max) at a voltage that leads to reasonably long lifetime and increase the capacitor utilization ratio of the supercapacitor stack. the capacitor utilization ratio, b , can be defined as: b = cell(max) 2 v C cell(min) 2 v cell(max) 2 v if the synchronous controller in step-up mode is used then the supercapacitors can be run down to a voltage set by the ltc 3350 3350fb for more information www.linear.com/ltc3350
26 a pplica t ions i n f or m a t ion maximum power transfer rule to maximize the utilization ratio. the minimum voltage in this case is: v cell(min) = 4r sc ? p backup n where is the efficiency of the boost converter (~90% to 96%). for the backup equation, max and min , substitute p backup / for p backup . in this case the energy needed for backup is governed by the following equation: p backup t backup 1 2 nc sc ? cell(max) 2 v ? b + b 2 C 1C b 2 ln 1 + b 1C b ? ? ? ? ? ? ? ? ? ? ? ? ? ? once a capacitance is found using the above equation the maximum esr allowed needs to be checked: r sc 1C b ( ) n cell(max) 2 v 4p backup capacitor selection procedure 1. determine backup requirements p backup and t backup . 2. determine maximum cell voltage that provides accept- able capacitor lifetime. 3. choose number of capacitors in the stack. 4. choose a desired utilization ratio, b , for the superca- pacitor (e.g., 80%). 5. solve for capacitance, c sc : c sc 2p backup ? t backup n cell(max) 2 v ? b + b 2 C 1C b 2 ln 1 + b ( ) 1C b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? C1 6. find supercapacitor with sufficient capacitance c sc and minimum r sc : r sc 1C b ( ) n cell(max) 2 v 4p backup 7. if a suitable capacitor is not available, iterate by choosing more capacitance, a higher cell voltage, more capacitors in the stack and/or a lower utilization ratio. 8. make sure to take into account the lifetime degrada - tion of esr and capacitance, as well as the maximum discharge current rating of the supercapacitor. a list of supercapacitor suppliers is provided in table 2. table 2. supercapacitor suppliers avx www.avx.com bussman www.cooperbussman.com cap-xx www.cap-xx.com illinois capacitor www.illcap.com maxwell www.maxwell.com ness cap www.nesscap.com tecate group www.tecategroup.com inductor selection the switching frequency and inductor selection are in- terrelated. higher switching frequencies allow the use of smaller inductor and capacitor values, but generally results in lower efficiency due to mosfet switching and gate charge losses. in addition, the effect of inductor value on ripple current must also be considered. the inductor ripple current decreases with higher inductance or higher frequency and increases with higher v in . accepting larger values of ripple current allows the use of low inductances but results in higher output voltage ripple and greater core losses. for the ltc3350, the best overall performance will be attained if the inductor is chosen to be: l = v in(max) i chg(max) ? f sw for v in(max) 2v cap and: l = 1C v cap v in(max) ? ? ? ? ? ? v cap 0.25 ? i chg(max) ? f sw for v in(max) 2v cap , where v cap is the final supercapaci- tor stack voltage, v in(max) is the maximum input voltage, i chg(max) is the maximum regulated charge current, and f sw is the switching frequency. using these equations, the inductor ripple will be at most 25% of i chg(max) . ltc 3350 3350fb for more information www.linear.com/ltc3350
27 using the above equation, the inductor may be too large to provide a fast enough transient response to hold up v out when input power goes away. this occurs in cases where the maximum v in can be high (e.g. 25 v) and the backup voltage low (e.g. 6 v). in these situations it would be best to choose an inductor that is smaller resulting in maximum peak- to- peak ripple as high as 40% of i chg( max) . once the value for l is known, the type of inductor core must be selected. ferrite cores are recommended for their very low core loss. selection criteria should concentrate on minimizing copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this causes an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate. the saturation current for the inductor should be at least 80% higher than the maximum regulated current, i chg(max) . a list of inductor suppliers is provided in table 3. table 3. inductor vendors vendor url coilcraft www.coilcraft.com murata www.murata.com sumida www.sumida.com tdk www.tdk.com toko www.toko.com vishay www.vishay.com wrth electronic www.we-online.com c out and c cap capacitance v out serves as the input to the synchronous controller in step-down mode and as the output in step-up ( backup) mode. if step-up mode is used, place 100 f of bulk (aluminum electrolytic, os-con, poscap) capacitance for every 2 a of backup current desired. for 5 v system applications, 100 f per 1 a of backup current is recom - mended. in addition, a certain amount of high frequency bypass capacitance is needed to minimize voltage ripple. the voltage ripple in step-up mode is: ? v out = 1C v cap v out ? ? ? ? ? ? 1 c out ? f sw + v out v cap ? r esr ? ? ? ? ? ? i out(backup) maximum ripple occurs at the lowest v cap that can supply i out(backup) . multilayer ceramics are recommended for high frequency filtering. if step-up mode is unused, then the specification for c out will be determined by the desired ripple voltage in step-down mode: ? v out = v cap v out 1C v cap v out ? ? ? ? ? ? i chg(max) c out ? f sw + i chg(max) ? r esr in continuous conduction mode, the source current of the top mosfet is a square wave of duty cycle v cap /v out . to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms ? i chg(max) v cap v out v out v cap C 1 this formula has a maximum at v out = 2 v cap , where i rms = i chg(max) /2. this simple worst-case condition is commonly used for design because even significant devia - tions do not offer much relief. medium voltage (20 v to 35 v) ceramic, tantalum, os-con, and switcher-rated electrolytic capacitors can be used as input capacitors. sanyo os-con svp, svpd series, sanyo poscap tqc series, or aluminum electrolytic capacitors from panasonic wa series or cornel dublilier spv series in parallel with a couple of high performance ceramic capacitors can be used as an effective means of achieving low esr and high bulk capacitance. v cap serves as the input to the controller in step-up mode and as the output in step-down mode. the purpose of the v cap capacitor is to filter the inductor current ripple. the v cap ripple (?v cap ) is approximated by: ? v cap ? i pp 1 8c cap ? f sw + r esr ? ? ? ? ? ? where f sw is the switching frequency, c cap is the ca- pacitance on v cap and ?i pp is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i pp increases with input voltage. a pplica t ions i n f or m a t ion ltc 3350 3350fb for more information www.linear.com/ltc3350
28 a pplica t ions i n f or m a t ion because supercapacitors have low series resistance, it is important that c cap be sized properly so that the bulk of the inductor current ripple flows through the filter capaci- tor and not the supercapacitor. it is recommended that: 1 8c cap ? f sw + r esr ? ? ? ? ? ? n ? r sc 5 where n is the number of supercapacitors in the stack and r sc is the esr of each supercapacitor. the capacitance on vcap can be a combination of bulk and high frequency capacitors. aluminum electrolytic, os-con and poscap capacitors are suitable for bulk capacitance while multilayer ceramics are recommended for high frequency filtering. power mosfet selection tw o external power mosfets must be selected for the ltc3350s synchronous controller: one n-channel mosfet for the top switch and one n-channel mosfet for the bottom switch. the selection criteria of the external n- channel power mosfets include maximum drain- source voltage ( v dss ), threshold voltage, on - resistance ( r ds ( on ) ), reverse transfer capacitance ( c rss ), total gate charge ( q g ), and maximum continuous drain current. v dss of both mosfets should be selected to be higher than the maximum input supply voltage ( including transient). the peak-to-peak drive levels are set by the drv cc voltage. logic-level threshold mosfets should be used because drv cc is powered from either intv cc (5v) or an external ldo whose output voltage must be less than 5.5v. mosfet power losses are determined by r ds(on) , c rss and q g . the conduction loss at maximum charge current for the top and bottom mosfet switches are: p cond(top) = v cap v out i chg(max) 2 ? r ds(on) 1 + ? t ( ) p cond(bot) = 1C v cap v out ? ? ? ? ? ? i chg(max) 2 ? r ds(on) 1 + ? t ( ) the term (1+ ? t) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. both mosfet switches have conduction loss. however, transition loss occurs only in the top mosfet in step- down mode and only in the bottom mosfet in step-up mode. these losses are proportional to v out 2 and can be considerably large in high voltage applications (v out > 20v). the maximum transition loss is: p tran k 2 v out 2 ? i chg(max) ? c rss ? f sw where k is related to the drive current during the miller plateau and is approximately equal to one. the synchronous controller can operate in both step- down and step-up mode with different voltages on v out in each mode. if v out is 12 v in step-down mode ( input power available) and 10v in step-up mode (backup mode) then both mosfets can be sized to minimize conduction loss. if v out can be as high as 25 v while charging and v out is held to 6 v in backup mode, then the mosfets should be sized to minimize losses during backup mode. this may lead to choosing a high side mosfet with significant transition loss which may be tolerable when input power is avail - able so long as thermal issues do not become a limiting factor. the bottom mosfet can be chosen to minimize conduction loss. if step- up mode is unused, then choosing a high side mosfet that that has a higher r ds(on) device and lower c rss would minimize overall losses. another power loss related to switching mosfet selection is the power lost to driving the gates . the total gate charge, q g , must be charged and discharged each switching cycle. the power is lost to the internal ldo and gate drivers within the ltc3350. the power lost due to charging the gates is: p g (q gtop + q gbot ) ? f sw ? v out where q gtop is the top mosfet gate charge and q gbot is the bottom mosfet gate charge. whenever possible, utilize mosfet switches that minimize the total gate charge to limit the internal power dissipation of the ltc3350. schottky diode selection optional schottky diodes can be placed in parallel with the top and bottom mosfet switches. these diodes clamp sw during the non-overlap times between conduction of the top and bottom mosfet switches. this prevents the ltc 3350 3350fb for more information www.linear.com/ltc3350
29 a pplica t ions i n f or m a t ion body diodes of the mosfet switches from turning on, storing charge during the non-overlap time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . one or both diodes can be omit- ted if the efficiency loss can be tolerated. the diode can be rated for about one-third to one-fifth of the full load current since it is on for only a fraction of the duty cycle. larger diodes result in additional switching losses due to their larger junction capacitance. in order for the diodes to be effective, the inductance between them and the top and bottom mosfets must be as small as possible. this mandates that these components be placed next to each other on the same layer of the pc board. top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the bst pin supplies the gate drive voltage for the top mosfet. capacitor c b , in figure 8, is charged though an external diode, d b , from drv cc when the sw pin is low. the value of the bootstrap capacitor, c b , needs to be 20 times that of the total input capacitance of the top mosfet. with the top mosfet on, the bst voltage is above the system supply rail: v bst = v out + v drvcc the reverse break down of the external diode, d b , must be greater than v out(max) + v drvcc(max) . the step-up converter can briefly run nonsynchronously when used in conjunction with the output ideal diode. dur - ing this time the bst to sw voltage can pump up to voltages exceeding 5.5 v if d b is a schottky diode. fast switching pn diodes are recommended due to their low leakage and junc - tion capacitance . a schottky diode can be used if the step- up converter runs synchronous throughout backup mode. intv cc / drv cc and ic power dissipation the ltc3350 features a low dropout linear regulator (ldo) that supplies power to intv cc from the v out sup- ply. int v cc powers the gate drivers ( when connected to drv cc ) and much of the ltc3350s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5 v. the ldo can supply a maximum current of 50 ma and must be bypassed to ground with a minimum of 1 f when not connected to drv cc . drv cc should have at least a 2.2 f ceramic or low esr electrolytic capacitor. no matter what type of bulk capacitor is used on drv cc , an additional 0.1f ceramic capacitor placed directly adjacent to the drv cc pin is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3350 to be exceeded. the intv cc current, which is dominated by the gate charge current, is supplied by the 5v ldo. power dissipation for the ic in this case is highest and is approximately equal to (v out ) ? ( i q + i g ), where i q is the non-switching quiescent current of ~4 ma and i g is gate charge current. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the i g supplied by the intv cc ldo is limited to less than 42 ma from a 35 v supply in the qfn package at a 70c ambient temperature: t j = 70c + (35v)(4ma + 42ma)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the intv cc ldo current must be checked while operating in continuous conduction mode at maximum v out . the power dissipation in the ic is drastically reduced if drv cc is powered from an external ldo. in this case the power dissipation in the ic is equal to power dissipation due to i q and the power dissipated in the gate drivers, (v drvcc ) ? ( i g ). assuming the external drv cc ldo output is 5 v and is supplying 42 ma to the gate drivers, the junc- tion temperature rises to only 82c: t j = 70c + [(35v)(4ma)+(5v)(42ma)](34c/w) = 82c figure 8. bootstrap capacitor/diode and drv cc connections bst sw >2.2f 3350 f07 d b drv cc intv cc ltc3350 c b 0.1f 1f opt ltc 3350 3350fb for more information www.linear.com/ltc3350
30 a pplica t ions i n f or m a t ion the external ldo should be powered from v out . it must be enabled after the intv cc ldo has powered up and its output must be less than 5.5 v. intv cc should no longer be tied to drv cc . minimum on-time considerations minimum on-time, t on(min) , is the smallest time dura- tion that the ltc3350 is capable of turning on the top mosfet in step-down mode. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. the minimum on-time for the ltc3350 is approximately 85 ns. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v cap v out ? f sw if the duty cycle falls below what can be accommodated by the minimum on- time, the controller will begin to skip cycles. the charge current and v cap voltage will continue to be regulated, but the ripple voltage and current will increase. ideal diode mosfet selection an external n- channel mosfet is required for the input and output ideal diodes. important parameters for the selection of these mosfets are the maximum drain-source voltage, v dss , gate threshold voltage and on-resistance ( r ds(on) ). when the input is grounded, either the supercapacitor stack voltage or the step - up controller s backup voltage is applied across the input ideal diode mosfet. therefore, the v dss of the input ideal diode mosfet must withstand the maximum voltage on v out in backup mode. when the supercapaci- tors are at 0 v, the input voltage is applied across the output ideal diode mosfet. therefore, the v dss of the output ideal diode mosfet must withstand the highest voltage on v in . the gate drive for both ideal diodes is 5 v. this allows the use of logic-level threshold n-channel mosfets. as a general rule, select mosfets with a low enough r ds(on) to obtain the desired v ds while operating at full load current. the ltc3350 will regulate the forward voltage drop across the input and output ideal diode mosfets to 30mv if r ds( on) is low enough. the required r ds( on) can be calculated by dividing 0.030 v by the load current in amps. achieving forward regulation will minimize power loss and heat dissipation, but it is not a necessity. if a forward volt- age drop of more than 30 mv is acceptable, then a smaller mosfet can be used but must be sized compatible with the higher power dissipation. care should be taken to ensure that the power dissipated is never allowed to rise above the manufacturers recommended maximum level. during backup mode, the output ideal diode shuts off when the voltage on outfb falls below 1.3 v. for high v out backup voltages (>8.4 v), the output ideal diode will shut off when v cap is more than a diode drop (~700mv) above the v out regulation point ( i.e., outfb > 1.2 v). the body diode of the output ideal diode n-channel mosfet will carry the load current until v cap drops to within a diode drop of the v out regulation voltage at which point the synchronous controller takes over. during this period the power dissipation in the output ideal diode mosfet increases significantly. diode conduction time is small compared to the overall backup time but can be significant when discharging very large supercapacitors (>600f ). care should be taken to properly heat sink the mosfet to limit the temperature rise. pcb layout considerations when laying out the printed circuit board, the following guidelines should be used to ensure proper operation of the ic. check the following in your layout: 1. keep mn1, mn2, d 1, d 2 and c out close together. the high di/dt loop formed by the mosfets, schottky diodes and the v out capacitance, shown in figure?9, should have short, wide traces to minimize high frequency noise and voltage stress from inductive ringing. surface mount components are preferred to reduce parasitic inductances from component leads. figure 9. high speed switching path + + + + high frequency circulating path mn2 mn1 v out d2 d1 c cap 3350 f09 c out r snsc v cap l1 ltc 3350 3350fb for more information www.linear.com/ltc3350
31 a pplica t ions i n f or m a t ion connect the drain of the top mosfet and cathode of the top diode directly to the positive terminal of c out . connect the source of the bottom mosfet and anode of the bottom diode directly to the negative terminal of c out . this capacitor provides the ac current to the mosfets. 2. ground is referenced to the negative terminal of the v cap decoupling capacitor in step-down mode and to the negative terminal of the v out decoupling capacitor in step-up mode. the negative terminal of c out should be as close as possible to the negative terminal of c cap by placing the capacitors next to each other and away from the switching loop described above. the combined ic sgnd pin/pgnd paddle and the ground returns of c intvcc and c drvcc must return to the com- bined negative terminal of c out and c cap . 3. effective grounding techniques are critical for success - ful dc / dc converter layouts. orient power components such that switching current paths in the ground plane do not cross through the sgnd pin and exposed pad on the backside of the ltc3350 ic. switching path currents can be controlled by orienting the mosfet switches, schottky diodes, the inductor, and v out and v cap decoupling capacitors in close proximity to each other. 4. locate v cap and v out dividers near the part and away from switching components. kelvin the top of resistor dividers to the positive terminals of c cap and c out , respectively. the bottom of the resistive dividers should go back to the sgnd pin. the feedback resistor con - nections should not be run along the high current feeds from the c out capacitor. 5. route icap and vcap sense lines together, keep them short. same with voutsp and voutsn. filter com - ponents should be placed near the part and not near the sense resistors. ensure accurate current sensing with kelvin connections at the sense resistors. see figure?10. 6. the trace from the positive terminal of the input current sense resistor, r snsi , to the voutsp pin carries the parts quiescent and gate drive currents. to maintain accurate measurement of the input current keep this trace short and wide by placing r snsi near the part. 7. locate the drv cc and bst decoupling capacitors in close proximity to the ic. these capacitors carry the mosfet drivers high peak currents. an additional 0.1 f ceramic capacitor placed immediately next to the d rv cc pin can help improve noise performance substantially. 8. locate the small-signal components away from high frequency switching nodes ( bst, sw, tg, and bg). all of these nodes have very large and fast moving signals and should be kept on the output side of the ltc3350. 9. the input ideal diode senses the voltage between v in and voutsp. v in should be connected near the source of the input ideal diode mosfet. voutsp is used for kelvin sensing the input current. place the input cur - rent sense resistor, r snsi , near the input ideal diode mosfet with a short, wide trace to minimize resistance between the drain of the ideal diode mosfet and r snsi . 10. the output ideal diode senses the voltage between voutsn and vcap. vcap is used for kelvin sensing the charge current. place the output ideal diode near the charge current sense resistor, r snsc , with a short, wide trace to minimize resistance between the source of the ideal diode mosfet and r snsc . 11. the infet and outfet pins for the external ideal diode controllers have extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from these pins will introduce an additional offset to the ideal diodes of approximately 10mv. to minimize leakage, the infet trace can be guarded on the pc board by surrounding it with vout connected metal. similarly, the outfet trace should be guarded by surrounding it with vcap connected metal. figure 10. kelvin current sensing 3350 f10 direction of sensed current r snsc or r snsi to vcap or voutsn to icap or voutsp ltc 3350 3350fb for more information www.linear.com/ltc3350
32 r egis t er map register sub addr r/w bits description default page clr_alarms 0x00 r/w 15:0 clear alarms register 0x0000 33 msk_alarms 0x01 r/w 15:0 enable/mask alarms register 0x0000 33 msk_mon_status 0x02 r/w 9:0 enable/mask monitor status alerts 0x0000 34 cap_esr_per 0x04 r/w 15:0 capacitance/esr measurement period 0x0000 34 vcapfb_dac 0x05 r/w 3:0 v cap voltage reference dac setting 0xf 34 vshunt 0x06 r/w 15:0 capacitor shunt voltage setting 0x3999 34 cap_uv_lvl 0x07 r/w 15:0 capacitor undervoltage alarm level 0x0000 34 cap_ov_lvl 0x08 r/w 15:0 capacitor overvoltage alarm level 0x0000 34 gpi_uv_lvl 0x09 r/w 15:0 gpi undervoltage alarm level 0x0000 34 gpi_ov_lvl 0x0a r/w 15:0 gpi overvoltage alarm level 0x0000 34 vin_uv_lvl 0x0b r/w 15:0 v in undervoltage alarm level 0x0000 35 vin_ov_lvl 0x0c r/w 15:0 v in overvoltage alarm level 0x0000 35 vcap_uv_lvl 0x0d r/w 15:0 v cap undervoltage alarm level 0x0000 35 vcap_ov_lvl 0x0e r/w 15:0 v cap overvoltage alarm level 0x0000 35 vout_uv_lvl 0x0f r/w 15:0 v out undervoltage alarm level 0x0000 35 vout_ov_lvl 0x10 r /w 15:0 v out overvoltage alarm level 0x0000 35 iin_oc_lvl 0x11 r/w 15:0 i in overcurrent alarm level 0x0000 35 ichg_uc_lvl 0x12 r/w 15:0 i chg undercurrent alarm level 0x0000 35 dtemp_cold_lvl 0x13 r/w 15:0 die temperature cold alarm level 0x0000 35 dtemp_hot_lvl 0x14 r/w 15:0 die temperature hot alarm level 0x0000 35 esr_hi_lvl 0x15 r/w 15:0 esr high alarm level 0x0000 35 cap_lo_lvl 0x16 r/w 15:0 capacitance low alarm level 0x0000 35 ctl_reg 0x17 r/w 3:0 control register 0b0000 36 num_caps 0x1a r 1:0 number of capacitors configured C 36 chrg_status 0x1b r 11:0 charger status register C 36 mon_status 0x1c r 9:0 monitor status register C 37 alarm_reg 0x1d r 15:0 active alarms register 0x0000 37 meas_cap 0x1e r 15:0 measured capacitance value C 38 meas_esr 0x1f r 15:0 measured esr value C 38 meas_vcap1 0x20 r 15:0 measured capacitor one voltage C 38 meas_vcap2 0x21 r 15:0 measured capacitor two voltage C 38 meas_vcap3 0x22 r 15:0 measured capacitor three voltage C 38 meas_vcap4 0x23 r 15:0 measured capacitor four voltage C 38 meas_gpi 0x24 r 15:0 measured gpi pin voltage C 38 meas_vin 0x25 r 15:0 measured v in voltage C 38 meas_vcap 0x26 r 15:0 measured v cap voltage C 38 meas_vout 0x27 r 15:0 measured v out voltage C 38 meas_iin 0x28 r 15:0 measured i in current C 38 meas_ichg 0x29 r 15:0 measured i chg current C 38 meas_dtemp 0x2a r 15:0 measured die temperature C 38 registers at sub address 0x03, 0x18, 0x19, 0x2b-0xff are unused. ltc 3350 3350fb for more information www.linear.com/ltc3350
33 r egis t er descrip t ions clr_alarms (0x00) clear alarms register: this register is used to clear alarms caused by exceeding a programmed limit. writing a one to any bit in this register will cause its respective alarm to be cleared. the one written to this register is automatically cleared when its respective alarm is cleared. bit(s) bit name description 0 clr_cap_uv clear capacitor undervoltage alarm 1 clr_cap_ov clear capacitor overvoltage alarm 2 clr_gpi_uv clear gpi undervoltage alarm 3 clr_gpi_ov clear gpi overvoltage alarm 4 clr_vin_uv clear v in undervoltage alarm 5 clr_vin_ov clear v in overvoltage alarm 6 clr_vcap_uv clear v cap undervoltage alarm 7 clr_vcap_ov clear v cap overvoltage alarm 8 clr_vout_uv clear v out undervoltage alarm 9 clr_vout_ov clear v out overvoltage alarm 10 clr_iin_oc clear input overcurrent alarm 11 clr_ichg_uc clear charge undercurrent alarm 12 clr_dtemp_cold clear die temperature cold alarm 13 clr_dtemp_hot clear die temperature hot alarm 14 clr_esr_hi clear esr high alarm 15 clr_cap_lo clear capacitance low alarm msk_alarms (0x01) mask alarms register: writing a one to any bit in the mask alarms register enables its respective alarm to trigger an smbalert. bit(s) bit name description 0 msk_cap_uv enable capacitor undervoltage alarm 1 msk _cap_ov enable capacitor over voltage alarm 2 msk_gpi_uv enable gpi undervoltage alarm 3 msk_gpi_ov enable gpi overvoltage alarm 4 msk_vin_uv enable v in undervoltage alarm 5 msk_vin_ov enable v in overvoltage alarm 6 msk_vcap_uv enable v cap undervoltage alarm 7 msk_vcap_ov enable v cap overvoltage alarm 8 msk_vout_uv enable v out undervoltage alarm 9 msk_vout_ov enable v out overvoltage alarm 10 msk_iin_oc enable input overcurrent alarm 11 msk_ichg_uc enable charge undercurrent alarm 12 msk_dtemp_cold enable die temperature cold alarm 13 msk_dtemp_hot enable die temperature hot alarm 14 msk_esr_hi enable esr high alarm 15 msk_cap_lo enable capacitance low alarm ltc 3350 3350fb for more information www.linear.com/ltc3350
34 r egis t er descrip t ions msk_mon_status (0x02) mask monitor status register: writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an smbalert. bit(s) bit name description 0 msk_mon_capesr_active set the smbalert when there is a rising edge on mon_capesr_active 1 msk_mon_capesr_scheduled set the smbalert when there is a rising edge on mon_capesr_scheduled 2 msk_mon_capesr_pending set the smbalert when there is a rising edge on mon_capesr_pending 3 msk_mon_cap_done set the smbalert when there is a rising edge on mon_cap_done 4 msk_mon_esr_done set the smbalert when there is a rising edge on mon_esr_done 5 msk_mon_cap_failed set the smbalert when there is a rising edge on mon_cap_failed 6 msk_mon_esr_failed set the smbalert when there is a rising edge on mon_esr_failed 7 C reserved, write to 0 8 msk_mon_power_failed set the smbalert when there is a rising edge on mon_power_failed 9 msk_mon_power_returned set the smbalert when there is a rising edge on mon_power_returned 15:10 C reserved, write to 0 cap_esr_per (0x 04) 10 seconds per lsb capacitance and esr measurement period: this register sets the period of repeated capacitance and esr measurements. each lsb represents 10 seconds. capacitance and esr measurements will not repeat if this register is zero. vcapfb_dac (0x05) capfbref = 37.5mv ? vcapfb_dac + 637.5mv v cap regulation reference: this register is used to program the capacitor voltage feedback loops reference voltage. only bits 3:0 are active. vshunt (0x06) 183.5v per lsb shunt v oltage register: this register programs the shunt voltage for each capacitor in the stack. the charger will limit current and the active shunts will shunt current to prevent this voltage from being exceeded. as a capacitor voltage nears this level, the charge current will be reduced. this should be programmed higher than the intended final balanced individual capacitor voltage. setting this register to 0x0000 disables the shunt. cap_uv_lvl (0x07) 183.5v per lsb capacitor under voltage level: this is an alarm threshold for each individual capacitor voltage in the stack. if enabled, any capacitor voltage falling below this level will trigger an alarm and an smbalert. cap_ov_lvl (0x08) 183.5v per lsb capacitor over voltage level: this is an alarm threshold for each individual capacitor in the stack. if enabled, any capacitor voltage rising above this level will trigger an alarm and an smbaler t. gpi_uv_lvl (0x09) 183.5v per lsb general purpose input under voltage level: this is an alarm threshold for the gpi pin. if enabled, the voltage falling below this level will trigger an alarm and an smbalert. gpi_ov_lvl (0x0a) 183.5v per lsb general purpose input over voltage level: this is an alarm threshold for the gpi pin. if enabled, the voltage rising above this level will trigger an alarm and an smbalert. ltc 3350 3350fb for more information www.linear.com/ltc3350
35 r egis t er descrip t ions vin_uv_lvl (0x0b) 2.21mv per lsb v in undervoltage level: this is an alarm threshold for the input voltage. if enabled, the voltage falling below this level will trigger an alarm and an smbalert. vin_ov_lvl (0x0c) 2.21mv per lsb v in overvoltage level: this is an alarm threshold for the input voltage. if enabled, the voltage rising above this level will trigger an alarm and an smbalert. vcap_uv_lvl (0x0d) 1.476mv per lsb v cap undervoltage level: this is an alarm threshold for the capacitor stack voltage. if enabled, the voltage falling below this level will trigger an alarm and an smbalert. vcap_ov_lvl (0x0e) 1.476mv per lsb v cap overvoltage level: this is an alarm threshold for the capacitor stack voltage. if enabled, the voltage rising above this level will trigger an alarm and an smbalert. vout_uv_lvl (0x0f) 2.21mv per lsb v out undervoltage level: this is an alarm threshold for the output voltage. if enabled, the voltage falling below this level will trigger an alarm and an smbalert. vout_ov_lvl (0x10) 2.21mv per lsb v out overvoltage level: this is an alarm threshold for the output voltage. if enabled, the voltage rising above this level will trigger an alarm and an smbalert. iin_oc_lvl (0x11) 1.983v/r snsi per lsb input overcurrent level: this is an alarm threshold for the input current. if enabled, the current rising above this level will trigger an alarm and an smbalert. ichg_uc_lvl (0x12) 1.983v/r snsc per lsb charge undercurrent level: this is an alarm threshold for the charge current. if enabled, the current falling below this level will trigger an alarm and an smbalert. dtemp_cold_lvl (0x13) temperature = 0.028c per lsb C 251.4c die t emperature cold level: this is an alarm threshold for the die temperature. if enabled, the die temperature falling below this level will trigger an alarm and an smbalert. dtemp_hot_lvl (0x14) temperature = 0.028c per lsb C 251.4c die t emperature hot level: this is an alarm threshold for the die temperature. if enabled, the die temperature rising above this level will trigger an alarm and an smbalert. esr_hi_lvl (0x15) r snsc /64 per lsb esr high level: this is an alarm threshold for the measured stack esr. if enabled, a measurement of stack esr exceeding this level will trigger an alarm and an smbalert. cap_lo_lvl (0x16) 336f ? r tst /r t per lsb capacitance low level: this is an alarm threshold for the measured stack capacitance. if enabled, if the measured stack capacitance is less than this level it will trigger an alarm and an smbalert. when ctl_cap_scale is set to one the constant is 3.36 ? r tst /r t . ltc 3350 3350fb for more information www.linear.com/ltc3350
36 r egis t er descrip t ions ctl_reg (0x17) control register: several control functions are grouped into this register. bit(s) bit name description 0 ctl_strt_capesr begin a capacitance and esr measurement when possible; this bit clears itself once a cycle begins. 1 ctl_gpi_buffer_en a one in this bit location enables the input buffer on the gpi pin. with a zero in this location the gpi pin is measured without the buffer. 2 ctl_stop_capesr stops an active capacitance/esr measurement. 3 ctl_cap_scale increases capacitor measurement resolution by 100x, this is used when measuring smaller capacitors. 15:4 C reserved num_caps (0x1a) number of capacitors: this register shows the state of the cap_slct1, cap_slct0 pins. the value read in this register is the number of capacitors programmed minus one. value capacitors 0b00 1 capacitor selected 0b01 2 capacitors selected 0b10 3 capacitors selected 0b11 4 capacitors selected chrg_status (0x1b) charger status register: this register provides real time status information about the state of the charger system. each bit is active high. bit(s) bit name description 0 chrg_stepdown the synchronous controller is in step-down mode (charging) 1 chrg_stepup the synchronous controller is in step-up mode (backup) 2 chrg_cv the charger is in constant voltage mode 3 chrg _uvlo the charger is in under voltage lockout 4 chrg_input_ilim the charger is in input current limit 5 chrg_cappg the capacitor voltage is above power good threshold 6 chrg_shnt the capacitor manager is shunting 7 chrg_bal the capacitor manager is balancing 8 chrg_dis the charger is temporarily disabled for capacitance measurement 9 chrg_ci the charger is in constant current mode 10 C reserved 11 chrg_pfo input voltage is below pfi threshold 15:12 C reserved ltc 3350 3350fb for more information www.linear.com/ltc3350
37 r egis t er descrip t ions mon_status (0x1c) monitor status: this register provides real time status information about the state of the monitoring system. each bit is active high. bit(s) bit name description 0 mon_capesr_active capacitance/esr measurement is in progress 1 mon_capesr_scheduled waiting programmed time to begin a capacitance/esr measurement 2 mon_capesr_pending waiting for satisfactory conditions to begin a capacitance/esr measurement 3 mon_cap_done capacitance measurement has completed 4 mon_esr_done esr measurement has completed 5 mon_cap_failed the last attempted capacitance measurement was unable to complete 6 mon_esr_failed the last attempted esr measurement was unable to complete 7 C reserved 8 mon_power_failed this bit is set when v in falls below the pfi threshold or the charger is unable to charge. it is cleared only when power returns and the charger is able to charge. 9 mon_power_returned this bit is set when the input is above the pfi threshold and the charger is able to charge. it is cleared only when mon_power_failed is set. 15:10 C reserved alarm_reg (0x1d) alarms register: a one in any bit in the register indicates its respective alarm has triggered. all bits are active high. bit(s) bit name description 0 alarm_cap_ uv capacitor under voltage alarm 1 alarm_cap_ov capacitor overvoltage alarm 2 alarm_gpi_uv gpi undervoltage alarm 3 alarm_gpi_ov gpi overvoltage alarm 4 alarm_vin_uv v in undervoltage alarm 5 alarm_vin_ov v in overvoltage alarm 6 alarm_vcap_uv v cap undervoltage alarm 7 alarm_vcap_ov v cap overvoltage alarm 8 alarm_vout_uv v out undervoltage alarm 9 alarm_vout_ov v out overvoltage alarm 10 alarm_iin_oc input overcurrent alarm 11 alarm_ichg_uc charge undercurrent alarm 12 alarm_dtemp_cold die temperature cold alarm 13 alarm_dtemp_hot die temperature hot alarm 14 alarm_esr_hi esr high alarm 15 alarm_cap_lo capacitance low alarm ltc 3350 3350fb for more information www.linear.com/ltc3350
38 r egis t er descrip t ions meas_cap (0x1e) 336f ? r tst /r t per lsb measured capacitor stack capacitance value. when ctl_cap_scale is set to one the constant is 3.36f ? r tst /r t . meas_esr (0x1f) r snsc /64 per lsb measured capacitor stack equivalent series resistance (esr) value meas_vcap1 (0x20) 183.5v per lsb measured voltage between the cap1 and capr tn pins. meas_vcap2 (0x21) 183.5v per lsb measured voltage between the cap2 and cap1 pins. meas_vcap3 (0x22) 183.5v per lsb measured voltage between the cap3 and cap2 pins. meas_vcap4 (0x23) 183.5 v per lsb measured voltage between the cap4 and cap3 pins. meas_gpi (0x24) 183.5 v per lsb measurement of gpi pin voltage. meas_vin (0x25) 2.21 mv per lsb measured input voltage. meas_vcap (0x26) 1.476mv per lsb measured capacitor stack v oltage. meas_vout (0x27) 2.21mv per lsb measured output v oltage. meas_iin (0x28) 1.983v/r snsi per lsb measured input current. meas_ichg (0x29) 1.983 v/r snsc per lsb measured charge current. meas_dtemp (0x2a) temperature = 0.028c per lsb C 251.4c measured die temperature. ltc 3350 3350fb for more information www.linear.com/ltc3350
39 application circuit 1. 25v to 35v, 6.4a supercapacitor charger with 2a input current limit and 28v, 50w backup mode v in v dd si1555dl v in 25v to 35v 25v rising threshold 22v falling threshold infet mn1 sis434dn mn2 sis434dn l1 6.8h r snsc 0.005 r cap1 2.7 r cap2 2.7 r cap3 2.7 r cap4 2.7 r caprtn 2.7 mn3 sis434dn r snsi 0.016 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 80.6k d b b0540ws c b 0.1f c3 4.7f c4 0.1f c cap 47f r fbc1 866k r fbc2 118k c f 0.1f c cp5 0.1f cap1 5f cap1-4: nesscap eshsr-0005c0-002r7 l1: coilcraft xal7070-682me c fbo1 120pf c out2 10f 2 c out1 82f r fbo1 665k r fbo2 29.4k r pf2 4.53k r pf3 39.2k r3 10k r7 10k r4 100k c5 1f r6 121 r5 107k c c 1.2nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 28v 50w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta02 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst bgate + cap2 5f + cap3 5f + cap4 5f + + caprtn capfb typical a pplica t ions ltc 3350 3350fb for more information www.linear.com/ltc3350
40 application circuit 2. 11v to 20v, 16a supercapacitor charger with 6.4a input current limit and 10v, 60w backup mode v in v dd v in 11v to 20v infet mn1 sir422dp mn2 bsc026n02ks l1 2.2h r snsc 0.002 r cap1 2.7 r cap2 2.7 r cap3 2.7 r cap4 2.7 r caprtn 2.7 mn3 bsc046n02ks 2 r snsi 0.005 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 806k d b b0540ws c b 0.47f c3 4.7f c4 0.1f c cap 47f r fbc1 845k r fbc2 150k c f 0.1f c cp5 0.1f cap1 360f cap1-4: nesscap eshsr-0360co-002r7 l1: vishay ihlp5050fder2r2mo1 c fbo1 120pf c out2 22f 4 c out1 82f 4 r fbo1 619k r fbo2 89.5k r pf2 100k r3 10k r4 100k c5 1f r6 121 r5 133k c c 10nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 10v 60w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta03 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst bgate + cap2 360f + cap3 360f + cap4 360f + + caprtn capfb typical a pplica t ions application circuit 3. 11v to 20v, 5.3a lifepo 4 battery charger with 4.6a input current limit and 12v, 48w backup mode v in v dd v in 11v to 20v infet mn1 sis438dn mn2 bsz060ne2ls l1 3.3h r snsc 0.006 r cap1 3.6 r cap2 3.6 r cap3 3.6 r caprtn 3.6 v shunt = 3.6v l1: coilcraft xal7070-332me mn3 bsz060ne2ls r snsi 0.007 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 806k d b b0540ws c b 0.1f c3 4.7f c4 0.1f c cap 22f 4 r fbc1 909k r fbc2 118k c f 0.1f c cp5 0.1f c fbo1 120pf c out2 2.2f 2 c out1 47f 2 r fbo1 649k r fbo2 71.5k r pf2 100k r3 10k r4 100k c5 1f r6 10m r5 71.5k c c 4.7nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 12v 48w in backup tgate sw icap vcap cap_slct1 cap_slct0 vcapp5 3350 ta04 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst bgate caprtn capfb + + + ltc 3350 3350fb for more information www.linear.com/ltc3350
41 typical a pplica t ions application circuit 4. 11v to 35v, 4a supercapacitor charger with 2a input current limit and 10v, 1a backup mode application circuit 5. 11v to 20v, 4a supercapacitor charger with 2a input current limit and 5v, 2a backup mode v in v dd v in 11v to 35v infet mn1 sir426dp mn2 sir426dp l1 4.7h r snsc 0.008 r cap1 2.7 r cap2 2.7 r cap3 2.7 r cap4 2.7 r caprtn 2.7 mn3 sir426dp r snsi 0.016 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 806k d b 1n4448hwt c b 0.1f c3 4.7f d1 dfls240 c4 0.1f c cap 47f r fbc1 590k r fbc2 118k c f 0.1f c cp5 0.1f cap1 10f cap1-4: nesscap eshsr-0010c0-002r7 l1: vishay ihlp5050fder47mo1 c fbo1 100pf c out2 10f 2 c out1 82f r fbo1 665k r fbo2 90.9k r pf2 100k r3 10k r4 100k c5 1f r6 121 r5 107k c c 10nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 10v 10w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta05 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst c6 220pf bgate + cap2 10f + cap3 10f + cap4 10f + + caprtn capfb d2 dfls240 v in v dd v in 11v to 20v infet mn1 sir412dp mn2 sir426dp mn4 sir412dp l1 4.7h r snsc 0.008 r cap1 2.7 r cap2 2.7 r cap3 2.7 r cap4 2.7 r caprtn 2.7 mn3 sir426dp r snsi 0.016 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 806k d b 1n4448hwt c b 0.1f c3 4.7f d1 dfls240 c4 0.1f c cap 47f r fbc1 590k r fbc2 118k c f 0.1f c cp5 0.1f cap1 10f cap1-4: nesscap eshsr-0010c0-002r7 l1: vishay ihlp5050fder47mo1 c fbo1 100pf c out2 10f 2 c out1 82f r fbo1 665k r fbo2 210k r pf2 100k r3 10k r4 100k c5 1f r6 121 r5 107k c c 10nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 5v 10w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta06 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst c6 220pf bgate + cap2 10f + cap3 10f + cap4 10f + + caprtn capfb d2 dfls240 ltc 3350 3350fb for more information www.linear.com/ltc3350
42 typical a pplica t ions application circuit 6. 11 v to 15v , 2.3 a zeta- sepic high voltage capacitor charger with 2 a input current limit and 10v , 25 w backup mode v in v dd v in 11v to 15v infet mn1 fdmc7660s l1 4.7h r snsi 0.016 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 158k c b 0.1f c b2 4.7f c6 470pf 10f 10f 1 mp1 si7415dn mn2 fdmc86520l q1 si1555dl c3 4.7f c4 0.1f c7 10f r snsc 0.014 cap: nichicon uhw1v222mhd l1, l2: coilcraft xal4030-472me set ctl_cap_scale to 1 cap 2200f 35v 2 r captop 255k r capbot 20k r fbc1 787k r fbc3 604k c fbc 820pf r fbc2 28k c out 22f 5 r fbo1 768k r fbo2 100k r pf2 20k r3 10k c5 1f r6 10m r5 107k c c 22nf r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 10v 25w in backup tgate sw icap cap_slct0 cap_slct1 vcapp5 3350 ta07 cfp cfn cap4 cap3 cap2 cap1 sgnd pgnd itst rt vc gpi drv cc intv cc bst l2 4.7h bgate caprtn capfb + vcap in a zeta-sepic application there are several differences in the monitoring features due to differences in how the ltc3350 is configured. the capacitor voltage is measured differently, it is no longer measured in the meas_vcap register, but in the meas_vcap1 register. the scale factor for meas_vcap1 must be adjusted for the resistor divider connected to the cap1 pin. also in this configuration the precision current load ( itst) for the capacitance test cannot be used. the load on the capacitors are the external dividers only. a capacitance measurement may still be done. the results in the meas_cap_register will have an lsb in farads of: c lsb = C5.6 ? 10 C7 in 1C 0.2 v cap ? ? ? ? ? ? 1 + r captop r capbot ? ? ? ? ? ? ? ? ? ? ? ? r t r l where r l is the total resistance to ground in parallel with the capacitor, r captop is the top divider resistor from the capacitor to cap1 and r capbot is the bottom divider resistor from cap1 to ground. the above equation is for when the ctl _ cap _ scale bit is set to one. esr measurements may be possible with large capacitors with larger esrs. however, the accuracy of the esr measurement in this application is significantly reduced. the esr measurement in the meas_esr register must be scaled up by the resistor divider ratio. the voltage at the cap1 pin should be kept below the v shunt setting. ltc 3350 3350fb for more information www.linear.com/ltc3350
43 typical a pplica t ions application circuit 7. 4.8v to 12v, 10a supercapacitor charger with 6.4a input current limit and 5v, 30w backup mode v in v dd v in 4.8v to 12v 50s falling edge filter infet mn1 sis452dn mn2 sis452dn l1 1h r snsc 0.003 r cap1 2.7 r cap2 2.7 r caprtn 2.7 mn3 sis452dn r snsi 0.005 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 30.1k d b b0540ws c b 0.1f c3 10f c4 0.1f c cap 47f r fbc1 732k r fbc2 274k c f 0.1f c cp5 0.1f cap1 50f cap1-2: nesscap eshsr-0050c0-002r7 l1: coilcraft xal7030-102me c fbo1 100pf c out2 100f 6 c out1 2.2f 2 r fbo1 665k r fbo2 210k r pf2 10k 10pf mn4 si1062x 1m r3 1k r4 100k r c 2k c5 1f r6 121 r5 88.7k c c 4.7nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 5v 30w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta08 cfp cap4 cap3 cap2 cap1 cfn sgnd pgnd itst rt t vc gpi drv cc intv cc bst bgate + cap2 50f + caprtn capfb ltc 3350 3350fb for more information www.linear.com/ltc3350
44 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) ltc 3350 3350fb for more information www.linear.com/ltc3350
45 r evision h is t ory rev date description page number a 09/14 modified i rms equations in c out and c cap capacitance section changed 5v to 6v in back-up mode under the power mosfet selection section changed v cap voltage reference dac setting modified application circuit 27 28 32 42 b 01/15 remove v cmi common mode range from electrical characteristics remove conditions on i pfo falling and rising change analog-to-digital converter section change range in the general purpose input section to 0v to 5v change mn1 to mp1 just below figure 6 change m1, m2 to mn1, mn2 in the pcb layout considerations section increase page numbers to all entries on the register map for meas_vcap change v to mv change name to application circuit 6 4 5 18 20 23 30 32 38 42 ltc 3350 3350fb for more information www.linear.com/ltc3350
46 ? linear technology corporation 2014 lt 0115 rev b? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3350 r ela t e d p ar t s typical a pplica t ion 12v pcle backup controller part number description comments power management ltc3128 3a monolithic buck-boost supercapacitor charger and balancer with accurate input current limit 2% accurate average input current limit programmable to 3a, active charge balancing, charges 1 or 2 capacitors, v in range: 1.73v to 5.5v, v out range: 1.8v to 5.5v, 20-lead (4mm 5mm 0.75mm) qfn and 24-lead tssop packages ltc3226 2-cell supercapacitor charger with backup powerpath controller 1x/2x multimode charge pump supercapacitor charger, automatic cell balancing, powerpath, 2a ldo backup supply, automatic main/backup switchover, 2.5v to 5.5v, 16-lead 3mm 3mm qfn package ltc3355 20v, 1a buck dc/dc with integrated scap charger and backup regulator v in : 3v to 20v, v out : 2.7v to 5v, 1a main buck regulator, 5a boost backup regulator powered from single supercapacitor, overvoltage protection, 20- lead 4mm 4mm qfn package. ltc3625 1a high efficiency 2-cell supercapacitor charger with automatic cell balancing high efficiency step-up/step-down charging of tw o series supercapacitors. automatic cell balancing. programmable charging current to 500ma (single inductor), 1a (dual inductor). 12-lead 3mm 4mm dfn package ltc4110 battery backup system manager complete backup battery manager for li-ion/polymer, lead acid, nimh/ nicd batteries and supercapacitors. input supply range: 4.5v to 19v, programmable charge current up to 3a, 38-lead 5mm 7mm qfn package. ltc 4425 linear supercap charger with current-limited ideal diode and v/i monitor constant-current/constant-v oltage linear charger for 2-cell series supercapacitor stack. v in : li-ion/polymer battery, a usb port, or a 2.7v to 5.5v current-limited supply. 2a charge current, automatic cell balancing, shutdown current <2a. 12-pin 3mm 3mm dfn or 12-lead msop package v in v dd v in 11v to 20v infet mn1 sis438dn mn2 bsz060ne2ls mn4 sis438dn l1 3.3h r snsc 0.006 r cap1 2.7 r cap2 2.7 r cap3 2.7 r cap4 2.7 r caprtn 2.7 mn3 bsz060ne2ls r snsi 0.016 voutm5 voutsp ltc3350 voutsn outfet outfb pfi c1 0.1f c2 1f r pf1 806k d b 1n4448hwt c b 0.1f c3 4.7f c4 0.1f c cap 22f 4 r fbc1 866k r fbc2 118k c f 0.1f c cp5 0.1f cap1 10f c fbo1 120pf c out2 2.2f 2 c out1 47f 2 r fbo1 649k r fbo2 162k r pf2 100k r3 10k r4 100k c5 1f r6 121 r5 71.5k c c 10nf r t1 100k r2 10k r1 10k vcc2p5 pfo capgd smbalert scl sda pfo capgd smbalert scl sda v out 6v 25w in backup tgate sw icap vcap cap_slct0 cap_slct1 vcapp5 3350 ta09 cfp cap4 cap3 cap2 cap1 cfn gnd pgnd itst rt t vc gpi drv cc intv cc bst bgate + cap2 10f + cap3 10f + cap4 10f + caprtn capfb cap1-4: nesscap eshsr-0010c0-002r7 l1: coilcraft xal7030-332me ltc 3350 3350fb for more information www.linear.com/ltc3350

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